Is there a way to set a line to line (Electrical EC set) constraint for capacitance?
I have a large number of signal that have a maximum capacitance to a group of signals (channels) that can not exceed a small capacitance (in the order of 1 pF).
Currently I need to rote then do a parasitic measurement, then tweak the routing. The lengths can vary from less than1 inch to over 12inchs.
Thanks,
Wild
Hi
I am using ORCAD for PSPICE simulation. It works fine, but all of a sudden, this error happened: "ERROR(15053): Can not initialize PSpice UI"
I tried some method in this thread, but did not solve this problem.
(1) I renamed the %HOME%/cdssetup folder, then both Capture CIS and Pspice AD can not open, with a pop dialog "This application qiut...."
(2)I tried invok PSPICE from cmd window, after three pop window, the PSPICE AD enter into the correct window, but when I chose a simulation program, it quit again....as following picture
(3)copied both cdssetup folder and pspice.ini from my colleague, no help.
I am worried and I do not want to re-install the whole software.. Could you please help diagnose the problem? Thanks very much!!
@alokt
The footprint viewer functionality appears to be missing in OrCAD Capture 17.2. Can anyone else confirm and/or suggest a fix?
Hi,
Is there a way to re-order schematic page tabs?
I find it very confusing the way it works - especially when opening multiple projects where tabs from different projects can mix. currently for what I see tabs order depend solely on the order they were opened.
Thanks
That 17.20 uses multithreads I have seen when performing DRC-checks.
But is the software in general written to make use of multi-core/thread CPU's?
Planning ahead, I see that less cores and high speed vs many cores and low speed are
the general options when purchasing new computers (unless you want to buy the "extreme"
versions of I7 or the most expenceive Xeons,)
I have also compared some certified CAD Graphic boards (Nvidia Quadro)
vs boards intended for gaming (Geforce GTX 6xx, etc). Both these families sometimes
exhibits erratic behavior when displaying certain colors/outlines properly in some zoom levels.
I filed a case with Cadence regarding the turning on and off of layers, that it did not happend
until the mouse pointer was back in the board display area. This has been confirmed to be a problem
when using the Windows "Classic" skin (like w95) Once changing to W7 "Aero" look, the problem
was gone. I have not yet upgraded to W10, so I would like to know if this problem is gone
in W10?
We have a design where we have 2 nets that have different names but there are connected together at a common point.
We have added the 2 nets on the 'Allowed Global Shorts' but the PCB has them as 2 separate nets. And we cannot route them together. Why is this and how do we connect the 2 signals.
This is like AGND and DGND with a common connection point only.
I am not sure if I saw this question earlier, but why is the Cadence Tcl/tk Utilities not seen in accessories menu in OrCAD 17.2 ?
Please suggest what needs to be done
Thanks much
When I define a flex zone it automatically generates a Route Keepout shape on the layers that do not exist in the flex stackup. But these keepouts are exactly aligned with the edge of the flex region, which allows the dynamic planes in the rigid sections to go right to the edge. I could manually move the edges of all the keepout shapes on the plane layers to match the keepin area but this requires a manual edit on every edge of every plane layer. Is there some way to make the keepouts match automatically?
Hi,
I have created a heterogeneous part and I am using two of them in some of sheets in a design. Although I have used a uniqe part in two sheet, one of them fails in Annotation. I see below error message:
ERROR(ORCAP-1376): Cannot perform annotation of heterogeneous part 'U?C(Value AD9914) at location (2.80, 1.00) on page 07- DDS2 Power & CAPs', part has not been uniquely grouped (using a common User Property with differing Values) or the device designation has not been chosen
Thanks,
Hossein
Hi,
I have an annotated schematic with more than 2000 components. And I need to encapsulate the schematic in an hierarchical block but I would like to keep the old reference IDs.
Exists a way to create the hierarchical block without loosing the reference IDs? Or is there an (automatic) way to recover the old IDs?
Thank You
Martin
Hey guys...long time user of Capture CIS. We have always used MS Access to maintain our CIS database. After loading v17.2 and connecting to our .dbc and our CIS Database, we get an error as follows:
ERROR(ORCIS-6245): Database Operation Failed
Please Check Session For More Details
ERROR(ORCIS-6250): ODBC Error Code: -1
Description: The specified DSN contains an architecture mismatch between the Driver and Application
ODBC Error Description: State:IM014,Native:0,Origin:[Microsoft][ODBC Driver Manager]
After further investigation, it appears that error indicates a mismatch between 32-bit and 64-bit versions. We have made many attempts at changing our ODBC connection to correct this mismatch, but to no avail. Any thoughts or recommendations on fixing this would be appreciated.
Now what we noticed was the BenchAccess1720 sample file is, indeed, linked to an SQL database and NOT an Access database. I converted our Access Database over to an SQL database and managed to get things running again, however, this is NOT our preferred solution.
We are looking for a solution to get our MS Access database connected to CIS in v17.2 without any changes.
Has anybody else had to deal with this? I can't believe that we are the only ones having this issue.
Hello,
I try to Import my ADS Desgin in to the Allegro Desgin flow. but get some Errors.
Basicly i do the same as in the Video : www.youtube.com/watch.
I Start the Desgin Entry and I get the Error Message: ERROR(SPCOCN-1334): Library eesof_lib not found in cds.lib list.
When the Desgin has a Port, in additon the Error : WARNING(SPCOCN-515): Design Name: <symbols>DIPLEXER_V1.SCH.1.1 occure.
My guess is that the Ports are defined in eesof_lib, so I have only to add it. But where can get the lib?
I use Cadence Allegro 16.6-.2015 with RFoption And ADS 2015.01
I hope you can understand me, and thank You for you help.
Lars
What is the best solution for OrCAD/Allegro tool and within the OrCAD/Allegro family for PCB panelization. I need gerber output after performing panelization (which OrCAD Panel editor does not provide).
and Refdes of components should not get disturbed(Productivity tool box based panelization changes refdes by adding prefix)
Does Allegro Productivity tool box work with OrCAD PCB Professional license?
I am not able to see the Macro from the menu option is it still available in 17.2 version?
Thanks
Folks,
Have seen similar posts, but not exactly the same as I am experiencing. My version 16.2 Allegro has missing check boxes in the Film Control options tab within the Artwork Control Form dialog box. The layers of interest are there, but no check boxes allowing me individually select different layers to create/export gerber files.
I have seen discussions about deleting the pcbenv directory and letting Allegro re-establish, but still get the same issue on the Film Control tab of no check boxes.
Chris
Dears,
In one of my capsense design I need to implement the rotary slider (five segments). How can i recreate the same in PCB editor? Attached is for 3 segments a reference.
Need your valuable inputs,
Many Thanks
LN
I have an OrCAD Capture schematic that has a number of 1k resistors throughout the design. i need to replace many of them with 2.2k resistors. The parts are from a library (each value/type is an individual part, one part is a 1k 0402, another is a 2.2k 0402 etc), I am not using a CIS database. I can't replace/update the cached 1k part, as that would change all of the 1k parts in the design, and I only want to change some of them. Is there a way to do this within Capture, or does anyone have a TCL script that will allow me to do this? I want to preserve the REFDES when doing this replace, and not have to replace each part manually and then manually fix the REFDES.
Any help/suggestions appreciated,
Austin
I've recently been tasked to clean up and re-organize the whole library and found that there are multiple different naming conventions used for pad designs.
As allegro does not recognize "." there seems to be quite a problem when creating pads using millimeters instead of mils.
Here are some of my ideas for pad naming conventions:
rectangle pads (replacing "r" with "s" for square pads)
r0_6mmx1_6mm.pad
r161x30.pad (in mils)
circle pads ("p" for plated while "np" for non-plated)
c2_4mm_p1_2mm.pad
c2_4mm_np1_2mm.pad
c60p45.pad (in mils)
c60np45.pad
Any suggestions/sharing of experiences are most appreciated
Ken
I need to create a variant of my design (same pcb but different components fitted) but the variant editor does not appear in my SPB16.3 Project Manager.
What line do I need to add to the project flow to get the editor back again?
If I have a base design with Custom Variables like DWG_NUMBER, DWG_REVISION or BOARD_NAME which are populated for each variant with a different number revision etc. Is it possible to set these custom variables from within the Variant Editor? So that any variants can be output (printed) with the correct variant names and numbers?