I have a number of vias located close to a non plated hole and I do not get any errors. Even if I move A VIA insIde the hole AND I do not get any errors. I have all errors enabled. Any reason I do not get an error ?
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No DRC errors with a via located in a non plated hole.
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Active classes and sub-classes?
I am somewhat new to making PCBs and components, I am using this video as a guild to learning how to make footprints "(Please visit the site to view this video)
In the video, the first time she makes an assembly outline, she sets the class to Package geometry and the subclass to assembly_top, on the second chip however, when she draws the assembly outline, she uses the class of Board geometry and the subclass to silkscreen_top. I am not sure what the difference is, or which is even correct. Which class and subclass should be used to draw the assembly outline, silk screen, and package boundary?
EDIT: link to video above https://www.youtube.com/watch?v=pKVn8_TKanM
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List of classes
Hi,
I'm having trouble finding a reference that lists the various classes and subclasses in the PCB editor and their intended purpose.
For example, where can I draw lines and shapes that are used as a guide to the designer where to place components? In other words, there should be no other purpose or constraint on this class except to add shapes and text. Sort of like the silkscreen class.
Yanko
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List ambigous parts in tcl
For BOM generation I need to check if a BOM has ambiguous parts.
I have found no tcl examples for this.
How can I do this?
I only need to know if the there is an ambiguity, I don't need the affected parts.
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New 3D Canvas in Allegro
Does anyone know if there is a way to change the colors in the new 3D Canvas? I would like to make the board and components look more realistic. Like the board surface actually green...
Thanks
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Dbdoctor Error won't clear
I am getting an error when running dbdoctor and it won't clear. I have renamed the pad and eventually deleted it from my library but it don't go away. I'm Running PCB Designer 17.2 SO13. Any suggestions?
ERROR: in PAD STACK padstack name = SMD_1_17MM1_8
WARNING(SPMHA1-120): Illegal pad size.
Error cannot be fixed.
Thanks
Ryan
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(Rookie question) Delete a custom property from PARAM - special library (error 1141)
Hi everyone, I'm new to Orcad Capture and PSpice and currently trying to learn to use them.
I first started by reading this tutorial here "Introduction to OrCAD Capture and PSpice".
As explained in this tutorial (page 14-15), I used the part PARAM in the "special" library to be able to use parametric sweep. I followed the tutorial and added a new property to the part that I called "Rload".
But now the problem is that when I create a new project, the property is still there and I can't delete it (the value is hatched and I can't delete the complete row). I tried "delete property" but Capture raise the error ORCAP-1141.
I looked it up on Google and the forum but I found no answers. I am currently using Orcad Capture CIS Lite.
Any ideas? Thanks in advance.
EDIT: I just found out that the property "Rload" I added on the PARAM part is also added for any new part. For instance, if I create a new capacitor, it will also have the property "Rload".
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pspice simulation not proceeding further.
Hello,
while simulation in pspice ,simulation stuck in between and in the progress bar its showing Pwr Supplies = 50.0000
plz see below image-
what can be the issue and how to resolve it???
Regards
DC
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Pass Parameter Value to Hierarchical Schematic Part
I'm having trouble passing a parameter value to a hierarchical schematic part. Here are the details:
1. I created a library part with this PSpice Template definition: X^@REFDES %VCC+ %VCC- %+ %- %OUT @MODEL PARAMS: ?IDC|IDC=@IDC||IDC=1e-3|
2. In the library part I added a parameter called IDC, also with a default value of 1e-3
3. Then I created a hierarchical part with a schematic that has a DC current source value that I set to {IDC}
The problem is that unless I add to the hierarchical part schematic a PARAM block with a parameter called IDC and a value, my simulation of a design using the hierarchical part won't run (can't identify IDC parameter). But when I do add the PARAM block to the hierarchical part schematic, its value overrides the one in my simulation design schematic.
Ideas anyone?
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How to link matlab and pspice??
Hello,
how to link matlab and pspice??
and what can be done after linking matlab with pspice??
Regards
DC
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Netlisting error - part references across multiple instances of hierarchical blocks
I'm having problems going from OrCAD Capture to Allegro, I think due to multiple instances of hierarchical blocks... initially I got thousands of errors of the type:
ERROR(ORCAP-36035): Multiple pin 1's which have different nets connected for C1: PowerConditioner, PAGE1 (2.70, 1.80).
Even though the design netlists just fine when I try to simulate the circuit. I think this is because, when sending the netlist to pspice, it prefixes all references with the reference of the hierarchical block it appears in. So it's fine that I have a capacitor referenced as C1 inside basically every block. I tried renaming one of my C1 capacitors and that particular one disappeared from the error log.
After some searching I tried Annotating my design with the "unconditional" option set. This re-referenced all my components so that they have unique names (up to C1000 etc) on the schematic pages. However, I still have multiple instances of a fair number of hierarchical blocks (many of them appear 32 times, nested inside other multiply-appearing hierarchical blocks). So, even though each of those hierarchical blocks has a unique path of reference designations, I still get 899 of these errors. But at least it's not thousands anymore.
There must be an option/checkbox somewhere that I can select so that Capture passes a sensibly-constructed reference designation for each part to Allegro, based on the reference designation of the blocks it appears in, just like it does for pspice... but I can't find it... could somebody help? Thanks!
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Changing footprint text size in entire library
We've been looking into our silkscreen text sizes and found we can shrink them a bit. So we'd like to do this for every component in our library.
Is there a way to automate this? We'd want to change only the ref des text on the silkscreen layer, not text on other layers.
DRA files are binary so I can't use a script. I could do it in SKILL but how to rip through the library folder, open each footprint, run the SKILL script, save the footprint, and move on to the next footprint? There's probably an easy way that I didn't think about or of which I'm not aware.
Any help would be appreciated!
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Compare Netlist Files
Hello,
I have netlist file.I want to check which components have been added or removed from the previous version of netlist file.
Orcad Capture or Allegro PCB Design Tool, which one need to use for this type of solution. ?
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Create a DRC for Ref Des under part.
This there a way to create a DRC for Ref Des silkscreen inside a place_bound or DFA_bound shape? I'm tired of finding ref des hidden under a part after manufacturing.
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Donut Pad to Ground Connection
I am using the Pad Editor in Ver. 17.2-2016 S011 at the moment.
I am trying to create a Pad Stack for a Non-Plated Mounting Hole that has a Donut Pad on the Outer Layers to connect to Ground.
Chassis Ground are on Internal Layers so, within the Board, I will be placing a Via and then adding a Trace to the Copper Donut Pad.
Once I define the Outer Layers as a Donut, the Usage Options at the bottom the Summary Page adds "Enable connect by touch: No"
As I seem to need to use Touch, to connect it to a via, without a DRC violation, I am expecting that this should say "Yes".
Richard
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Adding Layers to a micro via design
Is there any information on what happens to the micro-vias when you add layers to the design.
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Allegro Design Entry, Text input window bug
When you place a text on a schematic there is a window to edit its pro
perties, and that window is cropped and not adjustable. Please fix this ASAP!
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How to merger boards in Orcad Panel Editor
Hi
Using Orcad Panel Editor. We make boards that have radios. We want to step and repeat the board to make a panel but want to include one impedance test coupon per panel.
In Orcad/Allegro we design one board with the coupon. When I import into panel editor is there a way to not step and repeat the coupon? Can I move it independently from the rest of the board?
If I make them two separate boards is there a way to import both into panel editor?
Thanks
Peter
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Capture CIS Database setup using Orcale 11g
Hi,
Can we setup Capture.ini file and DBC configuration file to link to database systems like Oracle 11g.
Regards,
Vinay
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searching just one forum
It looks like the search on the upper toolbar searches everything . Is there a local search on this new website to just search one forum ?
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