Hello everyone,
I am implementing a 2 layer PCB board using Cadence Allegro V-17.2. I am using a Current Sense probe that needs to go through a single hole in the PCB.
I need contacts on both layers but the hole needs to be "non-plated type" (to isolate metal on top and bottom layer).
I am not able to implement such a setting with the pad and hole (Using Cadence padstack editor).
Kindly, if someone could help me with this situation.
Thank you!
-Rahul
When using OrCAD Capture Lite, the "IC" option on capacitors and inductors is grayed out. This is a problem because I need to be able to set them to a value when doing the analysis. After searching online, I don't see any solution to get them operational. Is there some other option I have failed to check in order to use them? Please see below for an screen shot of the problem.
Thank you in advance for any help.
Best regards,
Ron
I have randomly been able to select symbols in Capture and then move the group of symbols all at once in Allegro. This happens randomly and I cannot seem to be able to duplicate it all the time. What am I doing wrong ?
I have a design and I need to create two different variants from the base design, so I have the core design and two variants.
I am able to create one of the variants by selecting in the core design which parts are not present. But I can only do this in the core design, the field is grayed out if I go to the individual variants, which means I can only select one set of components which are not present. Given I have not seen this issue in other forum posts and this is a common thing to do, there must be something in the way I am setting up my variants that is wrong.
Anybody have suggestions on how to fix this? My version is 16.5
Previously Orcad CIS user, fairly new to DE HDL.
In DE HDL,
1. Is there a feature where I can find and replace netnames?
2. How do I select just netnames or just pins or just symbols.
3. I have 2 DE HDL instances running. In one, somehow I seem to have gotten into a mode where I can click on the symbol and move it (without selecting edit->move). Can't seem to replicate this in the other instance.
4. What does the error "The value for the $split inst name or location property on instance: xxx, pathval: i2 is not specified"
Hello, I am fairly new to PCB design and am currently trying to make my own PCB. I am having trouble figuring out how to tell which pin is which on OrCAD Capture 16.6.
Above is a capacitor that is in my circuit, and the second picture the PIN tab for this capacitor. How should I read this? should I use the first column as the pin number, so pin 1 is positive? or should I use order, so it would call the first pin 0, and it is positive? The footprint shown was designed by me.
Above is another part in my circuit. On this part, the "Number" column has numbers in it instead of the polarity like the CAP...? The footprint shown was created by me, I am trying to match the footprint pins to those in the circuit. The simulation uses BD140 instead of MJE15034 because I do not have MJE15034 in my parts library, on the actual PCB however, MJE15034 will be used.
Above is a third part from my circuit. On this part, both the number and order start with zero. On the PCB editor, when you place a pin/(pad?) it starts at 1, does this mean the first column is all I need? Or do I use one of the other columns and re-number the pins in PCB editor to start at 0?which Column is used to identify the pin number? The simulation uses MJL21194 but the real part will be MJL4281, which I do not have in my parts library. Both MJL4281 and MJL4302 appear to have the same pinout, so I was planning on using the same footprint for both components, to same some time and not have to design another footprint.
Know I did this previously but can't remember how ..
I have annotated a user property from CIS to Allegro. I now want to select or highlight components using the user defend property and value.
How do I accomplish this?
Is there a way to make ratsnests draw straight lines between pins, instead of jogs?
Guys,
Is there a way to hide schematic symbol pin numbers without editing the schematic symbol itself? We use the CIS database and part manager, so if I make any changes to a symbol OrCad creates a new copy of the symbol in my local cache and points to that instead, which flags up as an error in Part Manager (source symbol mismatch).
For example, if all the resistors in the database have the schematic symbol RESISTOR - if I edit the part on my schematics to hide pin numbers, it will make the part point to RESISTOR10 for example and cause part manager to fail.
I could add an alternative symbol to the database, but for every single resistor or cap that's quite a hassle.
Is there a property I can add to the parts to hide this pin? There is an option to hide power pins with a part property, maybe there is something similar?
Cheers
Has anyone ever seen a similar error message to this when trying to open an OPJ file in a shared folder in Virtualbox? I'm not sure if the shared folder, or Virtualbox is directly responsible for this issue. If you did, is there any easy way to solve it, or do I need to keep my files on the local hard drive of the Virtual Machine?:
I have a layout part that I need to change pin numbers on. How can I change a pin number? If it's showing as pin 1 for example, and I want to change it to pin 1?
I've revised a part in my footprint library, and want to update thelayout file. How do I do that?
Is it possible to customize the Part Name, as it appears in pstxprt.dat (NETLIST generated by OrCad).
It seems to take several schematic part properties, such as footprint, symbol name, and others to create a really long and hopefully unique Part Name.
However, in my case the Part Name gets too long and then it gets truncated to something that doesn't make sense.
There is probably a field or config somewhere to set-up what properties are taken from OrCAD to create unique Part Name in the net list.
Thank you!
We have a problem. We are doing a small project that has the schematics in Orcad V3.22 format. We can run Orcad V3.22 to view the schematics but we cannot print them as no parallel ports available and no parallel port printers either. We have tried quite a few methods to try to print the schematics but the schematics do not print properly. Included in our efforts have been DOS printer captures that supposedly will then print to Windows USB printers but not entirely successful. We have tried NET USE to redirect from LPT but again not entirely successful. We have a old plotter conversion program but only has parallel port printer drivers to LPT ports. We have searched for viewers but none found.
We downloaded and installed Orcad Capture Lite 17.2 and it runs just fine (Win7 computer). Copied and modified SDT.CFG to the folder with the sch files (changed directories). Included the list of all LIB files found during running DRAFT /C (shows configuration). But everytime I try to load an SCH file, Capture starts the translation and crashes immediately.
Really need to be able to either print the schematics directly or load and convert using Capture Lite. Any help would be greatly appreciated and thanks in advance.
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Hi Everyone,
I have a PCB that has very different propagation velocities on the outer layers (microstrip) vs the inner layers (stripline).
As a result, total etch length is not enough to satisfy my timing requirements...I need to know the propagation delay.
I have found from this video ( https://www.youtube.com/watch?v=jM_rpbFND18 ) , that I can measure propagation delay between pin pairs.
This is great -- but it's unclear what propagation velocity is being assumed.
Does PCB editor work out the propagation velocities for each layer using the stack-up?
Anyone know the answer? *Fingers crossed*
Thx.
mistake
Note from moderator - this was part of another thread in the Custom IC Design forum but was inappropriate for that forum, so moved to the PCB Design forum.
Hi, can you explain one moment. I'm trying to get simple sin wave and use VSIN and simple resistor in my circuit, Voff=0V, Vamp=220V, Freq=60Hz, AC=220V.
And i have 0 volts in my circuit, what's wrong with this source?
Thank you
I've defned a via in my padstack library. How do I tell layout I want to use it? I tried finding a setting in preferences with no success.
I'm trying to get the top copper layer, solder mask, and paste masks to show together. This is usually always worked for me and the colors are blended together.
However now I'm looking at a board that doesn't do that if the pad size of the layers is identical. I checked a different board and it was the same problem, I think it's a global thing.
For example I have the solder mask selected red and the paste mask selected yellow. When the solder mask is a little bit larger than the paste, the colors are blended together as orange. However if the pad is the same, then I only see yellow even though I know there is red under it.
If I change the transparency sliders, it will change the overall transparency but still doesn't blend the colors of 2 or more visible layers. How can I fix this?
