how to create open track in pcb editor. please fully explain. thanaks
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how to make track with soldermask ?
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PCB Designer: How to unlock read-only keyboard shortcuts for setting script shortcuts with the alias / funckey command
Having recently upgraded to 17.2 from 16.6 there now seems to be more read-only keyboard shortcuts. For example CTRL+Z (~Z), CTL+S (~S) etc... that were not readonly in 16.6
When trying to set these in 17.2 I get the response: W- alias ~S is marked read-only, not changed.
This was not an issue with 16.6 and I would still like to use the same shortcuts I had setup previously. Is there a way to unlock this read only state in 17.7 for locked keyboard shortcuts?
Thanks
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A VERY Fundamental Problem
Folks,
I have learned a lot on how to use Allegro, but found that I cannot import a very simple four two lead component OrCAD schematic into Allegro!! This is fundamental, and I have checked the Library paths in Preferences and indeed, I have pointed at the DRA footprints like re0603 and r0805 and sip6 and they are there in the Symbols library, but when I attempt to import into a new Allegro layout, all of the components are present, but when I check one and try to place it in the open layout, it simply says " Symbol C0603 not found for component C1". Yet you go to symbols under the D:\ENGINEERING\Cadence\SPB_16.2\share\pcb\pcb_lib\symbols\ where I have the full set of DRA, PSM and TXT files for these very simple components and cannot get them to come into the layout.
Old Mouldy...what the hell am I missing here? Do you need to place a board outline first (weird if true) or some other step I am not doing correctly. BTW, it is version 16.2 and netlisting from the OrCAD schematic executed without any issues.
Chris
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PCB Part - Ref Des
Hello, a quick question - when creating a part and then assigning a Ref Des name to the -part I am using the default
"REF" (Silkscreen_Top) Ref Des button and the text on the Silkscreen_Top is "REF"
What are you using for the default Ref Des Text? When I build the schematic symbol I will assign a "U" to this part. How does it know that this U1 (for example) will be assigned to REF? when I package it for layout?
Thank you
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Negative Image Thermal Relief Pads
I've created all my artwork, and everything looks great except I'm not seeing my negative image thermal pads. How do I get them to appear?
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Fix BOM output that has multiple [ENTER's]
Hi Forum,
Exporting the BOM from a project, outputs the file with a lot of spread 'New Lines'
Attached a portion of the BOM
How can I fix it without going though each component and build them again?
| Bill Of Materials April 25,2017 20:31:46 | ||||||||||
| Item | Description | Quantity | Reference | Value | PCB Footprint | Option | Manufacturer | Manufacturer Part Number | ||
| ______________________________________________ | ||||||||||
| 1 | CAP SM 1206 100uF 20% 6.3V X5R MONOLITHIC CERAMIC | 27 | C1,C479,C480,C481,C482,C483,C484,C496,C497,C498,C499,C900,C901,C902,C903,C904,C905,C930,C931,C932,C933,C941,C942,C943,C944,C945,C946 | 100U | 1206 | MURATA | GRM31CR60J107ME39D | |||
| 2 | CAP SM 0805 10uF 10% 10V X7R MONOLITHIC CERAMIC | 5 | C8,C442,C443,C456,C457 | 10U | 805 | MURATA | GRM21BR71A106KE51L | |||
| 3 | CAP SM 0402 2.2nF (2200pF) 10% 50V X7R MONOLITHIC CERAMIC | 64 | C9,C10,C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,C31,C32,C33,C34,C35,C36,C37,C38,C39,C40,C41,C42,C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55,C56,C57,C58,C59,C60,C61,C62,C63,C64,C65,C66,C67,C68,C69,C70,C71,C72 | 0.22uF | 402 | Murata | GRM155R61A224KE19D | |||
| 4 | CAP SM 0402 0.1uF 10% 16V X7R MONOLITHIC CERAMIC | 55 | C73,C74,C80,C81,C82,C83,C87,C88,C89,C90,C94,C95,C96,C97,C101,C102,C108,C109,C127,C128,C129,C132,C133,C134,C135,C136,C137,C138,C141,C148,C152,C153,C154,C155,C156,C157,C161,C162,C163,C164,C165,C168,C169,C170,C171,C172,C173,C174,C191,C192,C193,C203,C204,C219,C220 | 0U1 | CS-0402 | MURATA | GRM155R71C104KA88D | |||
| 5 | CAP SM 0402 0.1uF 10% 16V X7R MONOLITHIC CERAMIC | 65 | C75,C76,C77,C78,C79,C84,C85,C86,C91,C92,C93,C98,C99,C100,C103,C104,C105,C106,C107,C110,C111,C112,C113,C114,C130,C131,C139,C142,C143,C144,C145,C146,C147,C149,C150,C151,C175,C176,C177,C178,C179,C180,C181,C182,C183,C184,C194,C195,C196,C197,C198,C199,C200,C205,C206,C207,C208,C209,C210,C211,C212,C221,C222,C223,C224 | 0U1 | CS-0402 | DNI | MURATA | GRM155R71C104KA88D | ||
| 6 | CAP SM 1206 100uF 20% 6.3V X5R MONOLITHIC CERAMIC | 4 | C122,C124,C140,C158 | 100U | CS-1206 | MURATA | GRM31CR60J107ME39D | |||
| 7 | CAP SM 1206 100uF 20% 6.3V X5R MONOLITHIC CERAMIC | 1 | C125 | 100U | CS-1206 | DNI | MURATA | GRM31CR60J107ME39D | ||
| 8 | 7 | C166,C548,C549,C550,C551,C552,C553 | CAPACITOR NON-POL | CS-1206 | DNI | |||||
| 9 | CAP, CER, 0.1UF, 16V, X7R, 10%, SMD, 0402 | 9 | C225,C226,C227,C228,C566,C567,C568,C569,C854 | 100nF | CAPC1005X55N | |||||
| 10 | Cap 100nF 16VDC 0402 Ceramic\X7R, RoHS | 9 | C229,C230,C233,C235,C239,C240,C241,C242,C243 | 100nF | CAPC1005X55N | Murata | GRM155R71C104KA88 | |||
| 16 | CAP SM 0402 1.0uF 20% 10V X5R CERAMIC | 3 | C287,C295,C297 | 1U0 | 402 | TDK | ||||
| C1005X5R1A105M | ||||||||||
| 17 | CAP SM 0603 10uF 20% 6.3V X5R MONOLITHIC CERAMIC | 2 | C302,C304 | 10U | 603 | MURATA | GRM188R60J106ME47D | |||
| 18 | CAP SM 0402 2.2nF (2200pF) 10% 50V X7R MONOLITHIC CERAMIC | 4 | C311,C490,C922,C963 | 2N2 | 402 | MURATA | GRM155R71H222KA01D | |||
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move schematic part using keyboard
Is their any option where in we can use keyboard to move the schematic part in Capture.
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How to export pin property for a large heterogeneous part?
Hi there,
We have a heterogeneous symbol with 20 parts(A-T) on several schematic pages, 1156 pins . We need to export every pin's properties: inluding pin number, pin name, net name, I/O type, I/O standard and some other user-defined properties.
Usually I sue "Edit Properties" by right click on one sch symbol part, as below picture, then I copy columns from cadence to an xls. If I still use this method for this big FPGA, I have to copy a lot of times, and errors may occur. Is it possible to exporting all 1156 pins's properties just in one time? Thanks very much!
I tried select SCH folder and use "Tools---->Exporting Properties", and got an EXP file, which does not contain full property info I need.
I also tried "Export FPGA" command, choose CVS, just get "pin number" and "net name" information, but very strange , I got no info about pin's direction, io standard and others.... Following is excerpt from cvs file, as you can see, only Pin Number and Signal Name is exported, other attributes is empty.
Pin Number, Signal Name, Direction, IO Standard, Drive (mA), Slew Rate, Termination, IOB Delay, Diff Type, Diff Pair, Swap Group
H12,DDR_BF_RST_N,,,,,,,,,,
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Unable to update symbols
I've been fighting this error for about a week without coming up with a solution. I'm trying to update a symbol in my layout with "Place>Update Symbols. It errors out and produces the following log file (I desperately need to solve this issue!)
:
Sat Apr 29 13:49:27 2017 Page 1
Update Symbols/Modules Logfile
Sat Apr 29 13:49:27 2017
------ Module Refresh Messages ------
SUMMARY: Updated 0 out of 0 modules
------ End Module Messages ------
(---------------------------------------------------------------------)
( )
( Refresh Symbol )
( )
( Drawing : 881-2021-a19.brd )
( Software Version : 17.2S012 )
( Date/Time : Sat Apr 29 13:49:28 2017 )
( )
(---------------------------------------------------------------------)
Sat Apr 29 13:49:28 2017 Page 1
------ Symbol Refresh Directives ------
Input design = 'C:/_Work/Scribner_Associates/881-2021_A3/881-2021-a19.brd'
Output design = ''
Update mechanical symbols = 'NO'
Update format symbols = 'NO'
Update package symbols = 'NO'
Update shape/flash symbols = 'NO'
Update symbol padstacks = 'YES'
Preserve padstacks replaced on pins = 'NO'
Reset symbol text and size locations = 'NO'
Reset Pin Escapes (fanouts) = 'NO'
Ripup Etch = 'NO'
Reset custom drill data = 'NO'
Symbol list file = 'C:/Users/Admin/AppData/Local/Temp/#Taaaaac12968.tmp'
------ Library Paths ------
PSMPATH = C:/Cadence/SPB_17.2/share/pcb/pcb_lib/symbols
C:/_Work/_Libraries/Allegro_PCB/PWB-Misc/
C:/_Work/_Libraries/Allegro_PCB/L-Capacitor/
C:/_Work/_Libraries/Allegro_PCB/L-Connector/
C:/_Work/_Libraries/Allegro_PCB/L-Diode/
C:/_Work/_Libraries/Allegro_PCB/L-IC/
C:/_Work/_Libraries/Allegro_PCB/L-Inductor/
C:/_Work/_Libraries/Allegro_PCB/L-Misc/
C:/_Work/_Libraries/Allegro_PCB/L-Relay/
C:/_Work/_Libraries/Allegro_PCB/L-Resistor/
C:/_Work/_Libraries/Allegro_PCB/L-Switch/
C:/_Work/_Libraries/Allegro_PCB/L-Transistor/
C:/_Work/_Libraries/Allegro_PCB/SMD-Capacitor/
C:/_Work/_Libraries/Allegro_PCB/SMD-Connectors/
C:/_Work/_Libraries/Allegro_PCB/SMD-Crystal/
C:/_Work/_Libraries/Allegro_PCB/SMD-Diode/
C:/_Work/_Libraries/Allegro_PCB/SMD-Fuse/
C:/_Work/_Libraries/Allegro_PCB/SMD-IC/
C:/_Work/_Libraries/Allegro_PCB/SMD-Inductors/
C:/_Work/_Libraries/Allegro_PCB/SMD-Misc/
C:/_Work/_Libraries/Allegro_PCB/SMD-Relay/
C:/_Work/_Libraries/Allegro_PCB/SMD-Resistors/
C:/_Work/_Libraries/Allegro_PCB/SMD-Switch/
C:/_Work/_Libraries/Allegro_PCB/SMD-Transistor/
symbols
C:/Cadence/SPB_17.2/share/local/pcb/symbols
C:/Cadence/SPB_17.2/share/pcb/allegrolib/symbols
C:/Cadence/SPB_17.2/share/local/pcb/padstacks/
.
..
../symbols
PADPATH = symbols
c:/cadence/spb_17.2/share/pcb/pcb_lib/symbols
c:/cadence/spb_17.2/share/local/pcb/padstacks
c:/cadence/spb_17.2/share/pcb/allegrolib/symbols
..
../symbols
------ Symbol Refresh Messages ------
'MPSS100-8' symbol starting to refresh:
ERROR(SPMHNI-254): Unable to load symbol, 'MPSS100-8': 'ERROR(SPMHA1-161): Cannot open the design database file ... run stand~
alone dbdoctor on the file.'.
due to WARNING(SPMHUT-127): Could not find padstack 043X080R_2.
------ Pad Stack Refresh Messages ------
'040X080R_1' pad stack refreshed successfully.
'040X080S_2' pad stack refreshed successfully.
----- Symbol Update Summary ----
Refresh symbol errors; due to these errors this design is NOT updated.
1 errors detected.
0 warnings detected.
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Placing mechanical parts for not found
When I try to place a mechanical part from "Place > Mechanical Symbol > Mechanical Symbol", I get the following messages:
E-Can't find window; form.plc_manual"
E-Form not found.
This DID work recently, but doesn't work now. What could I have changed to make this happen. More importantly, how can it be fixed??
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Batch changing Pin Number visibility
Using plain OrCAD 16.6, is there a way to change the pin number visibility on a large amount of library parts at once? When I export the library properties, this doesn't seem to be one of the available fields. To put it into context, I inherited a large library of resistors and they all have their pin numbers visible. I'd like to change them all without having to go into each part and toggling it one at a time. Thanks!
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OrCAD PCB 16.6 - copper heat sink for a DFN with no electrical connections
I need to attach a copper shape to the epad of a DFN for heat sinking purposes. Adding a static solid etch shape to the pad causes all kinds of DRC errors.
I'm new to 16.6 and it looks like I have several ways to do this:
- Ignore the DRC's.
- Make a region around the DFN and set up constraints that'll work.
- ???
I'm cleaning up a design that had this connected to ground, but it should be electrically isolated.
What's the best way to handle this?
Pic from data sheet attached.
Thanks.
Tom
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Automatically Updating Page Numbers in Capture
I added a new page to my existing schematic and it started over at page 1 of 1. I know I can manually change the page numbers. Is there an automated way to change the page numbers so they are all grouped together?
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Leader Line compute text
Hi,
I am wondering if anyone knows a way to add computed text to a leader line? The goal is to add the x or y data to a leader line to essentially mark coordinates. Looks like this might not be possible at this time but it would be nice if %x or %y were used similar to %v for the linear dimensions. I appreciate any advice.
Thanks
Jeff
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Ask for help about Capture TCL/TK command's usage( GetDBCName in CPMgtCfg class )
HI! Everyone!
I'm a starter and want to use Capture TCL/TK commands for doing some automate function in Capture Schematic design.
I want to update all the place-instances' user prop. from SQL server( config in DBC ). Maybe I can do it by "CTRL-L" command to LINK to database one by one, but so many instance...it's a hard work, so I need to make a TCL command and do it automately.
I think I need to get access to the database part which is config in "capture.ini" and "demo.dbc" files.
I don't know where can I start firstly, as there was less infomation, even searching in google. So, I learn about it in "OrCAD_Capture_TclTk_Extensions.pdf", and find something may help.
In the PDF, there is some functions about the database operation in CPMgtCfg class such as GetDBCName, GetFirstTable, GetNextTable...
But, I don't know how to use the functions, there is little details. Is there anyone help? Thanks a lot!
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DCF file imports
When using CM for a design, do the DCF files have to be full and complete or can I set up subset DCF files for things like an 6mil region, 8mil region and 10mil region and then only import these separate files as needed? So if a design only needs a 10mil constraint region I only import the 10mil DCF file?
If so, how do I set up a subset DCF file? Is it a manual edit?
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Creating a footprint with surface mount pads on top and bottom layers
I have run into a snag with creating an edge connector footprint that has pads on both the top and bottom layers of the board. I have defined an SMD padstack with only a BEGIN LAYER in the Pad Editor and placed the pins for the top layer. However, I cannot figure out how to place pins that should be on the bottom. I am using the PCB Editor and I'm trying to do this while creating a package symbol. Thanks for your help!
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Instrumentation amplifier Noise
Hello,
I am PhD student in embedded system and I am working on a project that deals with the design of instrumentation amplifiers based on current conveyors. The instrumentation amplifier has two very high impedances inputs and one output.
I request your help to understand the following sentence and to know how I can determine these different noises under PSpice. “Find the thermal and 1/f noise both as noise density and integrated noise (voltage and current).”
In addition, I would like to know how I could determine the power-supply rejection ratio (PSRR).
Regards.
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Enable Undo/Redo in Part Editor
In Orcad Capture when I edit symbol or part, any change will not trigger history. And Undo/Redo button are disabled.
Is there any option that can enable Undo/Redo in Part Editor?
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SOLVED: Thermal relief not being placed
Hi,
Thermal reliefs in my design aren't placed except if I put the thermal relief parameters to FULL CONTACT.
- I can't find anything to fix this in Constraint Manager --> Same Net Spacing
- There is no VOID_SAME_NET property attached to the shape
- In the padstacks the regular pad, thermal relief and anti pad all have the same value
There must be something I'm missing. I'm using Allegro 16.6 S072
Please help
SOLVED: the route keepin was placed incorrectly. Sorry
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