When I import a Mentor design into Allegro 16.6 all the ref des show as "$REF".
Is there a setting I am overlooking?
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Mentor import into Allegro
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Issue in internal layer thermal relief offset after creating a padstack in Pad Designer
Hello All,
I created one padstack for a through hole pin in Pad Designer, and this pad has some characteristics, as described below:
- On TOP and BOTTOM layers, the regular pads are oblong;
- In the inner layers, the regular pads have circle geometry;
- The Drill hole is not located in the center (0,0) of the oblong regular pads - It is moved 0.55 mm to the right side - So, the location of the Drill hole is (X=0.55;Y=0), related to the oblong pads (TOP and BOTTOM);
- In the inner layers: the regular pads, the thermal relieves and the anti-pads are also moved 0.55 mm to the right side in order for them to be aligned with the drill hole.
Considering that I used an offset of 0.55 mm to both the drill hole and the Internal Layer pads (reg pad, Thermal relief and Anti-Pad), the thermal relief connects (tie bars) shouldn't have any misalignment problems when connecting to internal copper areas (shapes). However, there's the misalignment problem when connecting to internal copper areas, as can be seen below:
Is this an issue that needs a fix? Is there a solve for this? Can anybody help me?
Any help will be apreciated!
Regards,
Gustavo
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Allegro PCB - Command window 'SYNTAX ERROR'
Hi
I have some error outputs every time I open Allegro PCB Designer either through a file (double-click) or by a Windows Shortcut.
I attach a small txt file with a dump of this "log".
Is any of these an indication of potential malfunctioning/ problem? Should I just ignore them?
Best Regards,
Andreas
community.cadence.com/.../Alllegro_5F00_command_5F00_window_5F00_errors_5F00_02122017.txt
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Orcad Capture Wire Right Mouse Click "More" sub-menu
In Orcad Capture,16.6 and 17.2 (currently S30), until not long ago, you could place and replace hierarchical ports and off-page connectors by right-clicking on the wire and choosing the "More" sub-menu. This stopped working for me, not clear when but not more than 1-2 months ago, and was replaced with some grayed out PSpice options (I don't have a PSpice license). That was a very useful feature. Is the problem specifically with my machine, or did Cadence stop supporting this? Helpful answers will be appreciated.
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which shape type (dynamic/static) to be used in negative power planes?
Q1. which shape type (dynamic/static) to be used in negative power planes and why?
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Mechanical pins in symbol that are changed to normal pins do not update.
I have a symbol that had 9 mechanical pins. I changed them to normal pins and when I update the symbol the mechanical pins do not update.
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Cross Section Editor Impedance Calculator
Hi All,
I am trying to use the impedance calculation in the Cross Section Editor. I have compared the results to other impedance calculators. Three different calculators give very consistent results, while the results from the Cross Section Editor differ greatly. Attached are screen shots from the Editor and Saturn PCB Design's Toolkit. The Saturn Toolkit results match the other two calculators I tried. Looking at the TOP layer, the single ended impedances are different, and the differential impedances are very different.
Should the dielectric constant for the top layer be 4.5? I read in another post that it should be 4.5 for the internal layers because the prepreg squishes around them, but what about the top? Dropping it to 3.33 brings the single ended impedance close to the other calculators, but not the differential. Why should that dielectric constant matter at all?
So, the question is: Why should I use/trust the CSE calculator when 3 others give consistent different results?
Thanks or any insight you can give!
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Length match diff pair from pin to via
Hello everyone,
Is it possible to length/propagation match traces from pin to via then via to pin? I know you can do the entire trace but there doesn't seem to be a way to do this without net scheduling. Any ideas?
Thx,
Aric
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Can you please rate my website design?
Hello there!
I am currently working on the design of this website: https://vironit.com/
Can you please leave any feedback? Would be good to listen to some opinions.
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Can I rebuild the pspice netlist from scratch?
I have a mixed-signal design with both simulated and non-simulated parts (marked with spsnetlist_ignore=true properties) . It was simulating fine, but at some point it stopped working - I would just get "no simulation data for marker" errors on many of the nets. Frustratingly, it would even show me the sort of glitching warnings I'm simulating to find (at times that make sense) but when I ask it to plot those warnings I get the same errors. It seems like it is simulating, but that there is a net name mismatch between the schematic and simulation. Similarly, some nets plot fine when I probe a pin, but not when I probe the wire. If I cut-and-paste a part out and back into the design it sometimes starts working better, sometimes worse.
I've tried re-annotating and re-netlisting with various options, as well as pushing tools > sync netgroup, cutting and pasting large portions of the design, and starting new simulation profiles. The data collection options in the simulation profile are set to collect everything but the internal sub-circuits. All this serves to make it work differently, but not necessarily better or worse - some nets start working, some stop working, whether I can access the information by probing the wire vs. pin changes, etc. It all seems really strange.
Here's a little example from the schematic, grey probes give the "no data" error, black probes work fine:
The whole schematic is like that.
I found this thread online:
which indicates I need to start from scratch, but I really hope that's not the case. Certainly there must be a way to just rebuild the pspice netlist from scratch?
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Unable to open OrCAD Panel Editor 17.2
When the panel editor is opened through OrCAD PCB editor(professional) only the tool pallete is available and the panel editor window is not seen.
Kindly help to resolve the issue.
Regards,
Chadga
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Dynamic shape prevents me from place or move a connect line.
After updating Orcad 16.6 to 17.20.031 I can no longer place or move a connect line where a dynamic shape is. If I remove a connect line the dynamic shape updates immediately to fill the space.To do any routing I have to remove the shape and make a new shape later.
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deleting all via's per net
Is there a way to delete all the vias assigned to a specific net? I feel there should be a way to do this. In the delete command, there is an options tab but I have not been able to find out any information on how this works.
Any help would be appreciated.
Michael
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Netgroups between hierarchical blocks
I understand the concept of netgroups between blocks as long as they are all the same nets. i.e. We create one netgroup and all the blocks has a netgroup aware port and connected together with a netgroup bus.
But what about different nets to each block? I have a hierarchical block for an SPI device duplicated twice (device A & device B), each block has a netgroup port SPI_BUS with four signals clk, miso, mosi, and cs. I also have two blocks with SPI masters that also use SPI_BUS netgroup ports. I want to connect master block A to device block A, and master block B to device block B.
If I just put down a SPI_BUS netgroup bus between the master and device, block A and block B end up all being the same nets. I can keep the nets separate if I create two unique netgroups SPI1 and SPI2 with the same signals as SPI_BUS then connect SPI1 between the A blocks and SPI2 to the B blocks. I don't have to change the ports on the blocks, just draw the bus with the new netgroups.
Is this the right way to use netgroups and hierarchical blocks? If I need to duplicate this four more times, that means I would need to create four more uniquely named netgroups.
Should I use unnamed netgroups in this case?
This seems to get complicated fast since I have another hierarchical block that must be duplicated 8 times and the netgroup has 25 signals.
Thanks,
Bryan
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PCB Layout and Schematic capture suite availability for Linux environment
Hi,
Last post regarding the same was about 4 years ago. Are there any products from cadence which covers Schematic Capture and PCB Layout which works in Linux ? If available, how can I get a trial version ?
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Capture CIS explorer, footprint not shown
Hi.
I am using Cadence 16.6 Capture CIS...
I have assigned footprint in the database, which is not shown in the CIS explorer.
Placing the part in the schematic AND "show footprint" works great...
If I open the footprints in PCB editor, say Save As.. saving using same name, and then it WORKS in CIS explorer....
How can this be???
Is there a easy way to do this, it very trivial to do this for a high number of footprints.
Thanks,
Martin C.
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Constraint manager--->DRC external rule Violation
Hi sir,
My project report lots of DRC about external rule.
I do not set any rule about external and I do not familiar with it.
I search it in HELP Document but i can not fix it.
How can i fix it or any thing I did it wrong by mistake?
Thanks.
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Create a schematic with a spreadsheet?
I need about 15 or 20 very simple PCBs. They are comprised of two to four 50-100 pin connectors. I am creating them from an existing excel spreadsheet listing connector numbers and pins. Is it possible to import this into Capture? If not, is there any quicker method to get to the finished PCB layout? Possibly create a netlist from the spreadsheet?
Thanks
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Drill to Drill same Net - thru hole and laser values need to be different.
For the current design I need to be able to set the drill to drill same net at 10 mils for thru hole and 5 mils for lazer vias. Is there a way this can be done ?
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Tips & Tricks, changing layers , fast end easy, keyboard shortcuts, scripts
Changing layers on a larger board, can take a lots of mouse clicks.
If you know what layers you need, keyboard short-cuts are great.
Created a bunch of scripts, that lets you easy add and subtract layers, what are current active.
Without walking the menu. Helps reduce the eyestrain too.
Of course, every board is different, when the board Stackup is
custom. So it would need some editing, to match the layer names.
But once that is done, it is pretty slick and fast. You know, when the
Engineer sits over your shoulder, breathes up your neck. And for
hours goes on, let's look at layer 22, then 4, then 23 and 22. And so
on. This is really helps big time. Rob
download the scripts and pdf from my blog
https://www.robspcb.com/blog-un/5
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