Hi,
I'm trying to delete a dimension that is not associated with an object. I have tried using the Dimension Environment and the Delete Dimensions select from the drop down, but it will not delete. Any ideas on what I can do to make this go away?
Thanks!
Susan
Hi.
When in EtchEdit mode or general edit mode for routing I notice that when routing is finished by selecting "Done" the settings in the find dialog
settings get blown out.
I am trying to maintain the relationship between adding etch with find after the fact. In other words after etch is added to the canvas I want the
find dialog to retain ( Cline Segs, Pins, Nets, Rats T etc ) so that those items are selectable for either info or basic editing after the fact.
Is there any way to accomplish this other than creating a macro for find entities ?.
Basic idea is to have find pre-checked for a given command such as routing etc.
Something like a "IF Done" at the macro level would be helpful too though I do not know if something like that is supported ? , Like execute
the macro, after done is selected as an action then the macro runs the part to check find dialog items.
Thanks Paul.
Once in a while I have a need to create a single sided layout. In 16.6, I was able to click “Modify design padstack- all instances” to switch pads over to non-plated holes. Now in 17.2 (S031) you can’t toggle to the unplated option. Even thou there is a pull down arrow to do so. So now my drill chart continues to read plated for a non-plated design. This confuses the suppliers unless I add a note stating holes for the design shall be un-plated. I have no need to build a separate pad stack library to support single sided designs because they are so uncommon for us. It is much easier to just change the setting in the design. I suspect that is a bug due to the re-write of the padstack utility. Please confirm or advise.
Cheers
I have a MAX file from Samtec, which should be a connector footprint. I've been searching for how to Import it but haven't found anything that makes sense.
Any help would be appreciated, thanks
Hello,
I am creating a PCB panel of 12 modules in allegro 16.2
1. When I place modules in the panel , refdes of components of module1 shown as for e.g. R1> 1_R1 , U1>1_U1 and of module2 as R1>2_R2 , U2>2_U2. I want my refdes as for module1 R1>R1.1 , U1>U1.1 same as for module2 R1>R1.2 , U1>U1.2. Please suggest if there is any option to do this.
2. Also when i refresh module by update symbols option all user assigned refdes changes to default system assigned refdes.
Please suggest solutions.
Hi, I have received a board from a customer with some modifications to do. At the same time there are some
same net errors that they want to get rid of. The customer does not want the errors to be waived. Example:
This is an example trace which crosses a shape void and provokes an error at one end of the trace. The error remains even if the same net
line to shape value is set to zero. Switching off same net checking is not an option.
Has anyone found a solution to this problem?
Hello,
How to do multi trace routing at the same time can anyone suggest it. Multi trace routing option comes under which version of pcb editor??
Hello,
Is there a tcl script somewhere for Accessories > Hierarchy Report > Export Hierarchy?
I'd like to use this a a starting point to write my own script that prints the ports at each level of the hierarchy and the nets that are connected to each port. (To be more specific, I'd like to only print the net/port pair when the names are different as a way to check schematics).
Thank you!
In OrCAD PCB Designer, when I perform an 'Update Symbols' for all symbols (footprints) in a design, I get back a warning that some symbols cannot be found in my directory search path.
On closer inspection I find that the symbols in question are not on our system but more importantly they are not used in the design anyway.
The symbols are under the "Shape and flash symbols" category.
How can I find and delete these symbols from the design?
Hi,
I want to add an excel table in for fabrication. Is there any automatic method or I have to manually create it.
Any help would be highly appreciated.
Thanks and Regards
Hi,
Is there any way to down rev from 17.2 to 16.6.
I have tried but it says down rev from 17.2 to lower versions not possible.
Kindly help.
Regards
Hi ,there,
My ORCAD runs well recently , but all of a sudden, today I got some error when trying to creat net list. Could anyone help on this? I really do not want to reinstall Cadence 16.6
Following is Netlist setup(default as usual) and Error Screen shot. In the error picture, after I click OK, Cadence stopped responsing and stucked, so I have to end it in windows task manager.
Thanks very much!
Hi,
Has persistent snap for Show Measure been removed from 17.2? I don't see it anymore but it is there for commands like move and copy. Was it by design?
Thanks, David
I have a Xilinx Zynq demo board Allegro brd file from around 2013 that I would like to convert to a format readable with Altium Designer. The Allegro ASCII format is supposed to be compatible to some degree. If you have both Allegro and Altium a more direct conversion is supposed to be possible.
If this is something you are willing to help with please let me know.
Thank you.
Hi,
I am using Allegro PCB Designer 17.2 and i'm designing a Rigid flex board. There are few problems which i am facing in this design.
1. After adding the multiple stackup say Flex1 and Flex2 along with primary. If i change the layer material of layer 2 in Flex1 ,the same material will be selected the primary stackup as well. I want to use two different material in flex and primary stackup. How can this be done?
2. The number of layers in Flex1 should be 2 and the number of layers in Flex2 should be 4. How can this be done?
Help me on this issue.
Regards,
Chadga
Hi,
I got my license generated on my Virtual Adaptor MAC Address. Now the LMtools is not detecting this MAC ID,it doesn't show up in Ethernet address under system systems of LMtools and i'm getting licensing error. Why is that so. What is the solution to this problem.
Please help me on this issue.
Regards,
Chadga.
I want my diff pairs set up as follows. (8 layer PCB) Allegro 16.6
Top and bottom 5.5mil width with a 10mil space
L3 and L6 5mil width and a 7mil space
I need 30mil PAIR TO PAIR
PROBLEM: When I set 30 mil as my min space I get DRC's within pairs because their spacing is 7 or 10.
I only get this problem on layers 3 and 6, Top and bottom diff pairs route as expected 10 mil space and 30mil pair to pair.
Any ideas?
I have a few dynamic shapes set up, and when I place some MOSFET packages on them, with multiple same net pins, only a couple auto-connect with thermal reliefs. Some are left unconnected and need to be manually connected. For instance:
Note the pins with orange and green arrows are not connecting. Do I need to update a DRC rule, a global shape parameter, or something else? I've tried playing around but haven't had any luck. Thanks!
I need to use place replicate to resuse one section of board , Which conditions should be met to do this? Shall i need to make similar Stackup,refdes,package symbol?
I have a design that had to be converted to our internal CIS database. In doing so, many of the footprints where slightly different. The result is that nearly every net in the design is no longer connected to its respective clines.
Is there an easy way of re-associating the cline segments to their respective nets?