Hi,
I want to know how can we perform cross talk analysis if i have one net running in 1st layer and the other net in the 2nd signal layer which are parallel to each other. how can we do this in Sig explorer. Because generally we can perform cross talk for two parallel nets on the same layer.
Regards,
Chadga
I am trying to do the SI analysis of the simple circuit, I was able to calculate the impedance of the microstrip lines but i need do the overall impedance calculation of the design & how it should be done.
Hello,
Is it possible to route two or more differential pair at same time??
Suggest if possible...
Hi sir
I put 5 pcs same PCB design in one panel.
I try to copy the first finished layout to another 4 pcs but the part reference come to R* or C* while they should be R1 or C1.
It should be complete COPY if in proper setting. I fail to find it.
I got a solution in Manufacture--Drafting--Create Detail to acheive it.
Does any other method to complete copy part reference in such case?
Hi, does anyone know what are these white triangles on the pins, and how to get rid of them? Thanks in advance.
My DRC status is still red, indicating a DRC error:
But when I run Tools > Update DRC, then Tools > Quick Reports > Design Rules Check (DRC) Report nothing shows up in the window. Same with Tools > Quick Reports > Design Rules Net Short Check (DRC) Report.
Is this a bug? Or is there somewhere else I can check to see if any design rules are broken?
SPB 17.2 has removed the CDSROOT env var, which I'd used to determine the installation folder. I used it in a post-install script which configured users' PCs.
Is there a way to determine the install location in 17.2? For now if the env var was blank I just input a text string, but that's ugly and a pain to maintain.
Thanks!
Hi,
I upgraded to the latest version of Orcad PCB designer - 17.2-2016 S0333 (1/22/2018) windows SPB 64-bit Edition
I am getting the following error when I launch the PCB designer. Any idea what to do?
Thanks.
Just saw this: https://orcadcloud.ema-eda.com/ema-eda
Looks like a scaled down version of Capture's desktop application in the browser. The information seems scarce around this. Anyone know what Cadence's intentions are here?
Hi
Im using Orcad 17.2 and the script used for exporting schematic pdf's is Ghost script gswin64c.exe. But Now i'm getting an error while exporting pdf which is,
ERROR: undefined
OFFENDING COMMAND: G2UBegin
STACK:
/Font
/TT15Ct00
Converter arguments : -sDEVICE=pdfwrite -sOutputFile=$::capPdfUtil::mPdfFilePath -dBATCH -dNOPAUSE $::capPdfUtil::mPSFilePath
Could you please help me to resolve this?
Hi, I am relatively new to ORCAD and I have a schematic which is on multiple pages and I have multiple nets that are having a random number assigned to them on different pages. For example, I have VDD_MUX on one page and then on the next page the net that connects to the VDD_MUX symbol has net name VDD_MUX_85685.
No matter how many times I try to remove that number at the end, it always comes back.
Can somebody please advise?
Thanks
I've been using the command console and grouping items for many things recently and thought i had a grasp on it, however there is something i ran into that i don't understand. I'll post the commands i used with comments on what i think is happening and where i don't understand.
GOAL: pre-select a box of component, wires and whatever else is inside, run a few console window command via a script and end up with a group that contains only the LOCATION properties of the components i selected that have such property.
====CONSOLE WINDOW======
set next a
find location (place all LOCATION properties on the page into GROUP A)
WARNING(SPCOCN-1200): Using group A
INFO(SPCOCN-1195): Group "A" contains: 0 bodies 19 properties 0 notes 0 wires 0 dots 0 images
find location (place all LOCATION properties on the page into GROUP B, this is currently just a copy of A, but will be turned into a "negative mask" to get what i want into GROUP A later)
WARNING(SPCOCN-1200): Using group B
INFO(SPCOCN-1195): Group "B" contains: 0 bodies 19 properties 0 notes 0 wires 0 dots 0 images
group c cxtgrp (using the mouse, i pre-selected a area of components [see image below] along with all the wires and power nets that were encapsulated, within this area are the LOCATION properties of the components i want to group together along with other various properties, nets, wires.. etc. GROUP C now contains all these items)
WARNING(SPCOCN-1200): Using group C
INFO(SPCOCN-1195): Group "C" contains: 10 bodies 17 properties 0 notes 10 wires 4 dots 0 images
exclude b c (this turn GROUP B into a group of only LOCATION that contains all LOCATIONS on the page excpet the ones that where in my pre-selected area)
WARNING(SPCOCN-1203): Excluding from group B
INFO(SPCOCN-1195): Group "B" contains: 0 bodies 19 properties 0 notes 0 wires 0 dots 0 images
INFO(SPCOCN-1195): Group "B" contains: 0 bodies 14 properties 0 notes 0 wires 0 dots 0 images (this is correct, there where 5 components in my selection that had a LOCATION property and the difference before and after (19-14=5) is the result of excluding these 5 properties. GROUP B is not a "negative mask" of the LOCATION properties i want)
WARNING(SPCOCN-1206): Not in this group
exclude a b (this should leave GROUP A with the 5 LOCATION properties i'm trying to group together.)
WARNING(SPCOCN-1203): Excluding from group A
INFO(SPCOCN-1195): Group "A" contains: 0 bodies 19 properties 0 notes 0 wires 0 dots 0 images
INFO(SPCOCN-1195): Group "A" contains: 0 bodies 5 properties 0 notes 0 wires 0 dots 0 images (This is the end result i expect where GROUP A contains the 5 LOCATION properties)
WARNING(SPCOCN-1196): Group "A" is empty. (This is the part i don't understand, i seemed to have had what i needed, but all of a sudden GROUP A is now empty????)
============================
I've also tried various other ways to obtain this GOAL all of which end in the same result. Towards the end of my console commands i get an INFO message saying that GROUP A contains the 5 properties i desire, followed by a WARNING message that GROUP A is empty. Why does GROUP A go empty? There are no other commands that i ran between the INFO and WARMING messages.
Hi All,
How to generate basenet report and Cref in cadence concept HDL ?? i generated but i got some issue in this file.Kindly help any one for this quries.
Spawning... creferhdl.exe -proj "D:\Projects\Another Projects\3 boards\07-Feb-18_RFID\Wrk\FNS-10-01-18\FNS-10-01-18\FNS\FNS_archive\FNS.cpm"
@(#)$CDS: Crefer version 16.6-S090 (v16-6-112HQ) 4/4/2017
Reading Design ...
Copyright 2011 Cadence Design Systems, Inc Cadence Design Systems.
Crefer 16.6-S090 (v16-6-112HQ) 4/4/2017
Copyright 2011 Cadence Design Systems, Inc
, Status (12):: Loading design 'fns_section'.
, Status (10):: Loading connectivity file 'D:\Projects\Another Projects\3 boards\07-Feb-18_RFID\Wrk\FNS-10-01-18\FNS-10-01-18\FNS\FNS_archive\worklib\fns_section\sch_1/fns_section.xcon'.
, Status (11):: Loading property file 'D:\Projects\Another Projects\3 boards\07-Feb-18_RFID\Wrk\FNS-10-01-18\FNS-10-01-18\FNS\FNS_archive\worklib\fns_section\sch_1\fns_section.dcf'.
, Status (121):: Validating physical part information for components in design 'fns_section'.
Reading hdl database (00:00:00.37)
D:\Projects\Another Projects\3 boards\07-Feb-18_RFID\Wrk\FNS-10-01-18\FNS-10-01-18\FNS\FNS_archive\worklib\fns_section\sch_1\page1.csb: No known page border found.
If page borders other than those provided in standard library are used, please specify these in the cref data file
Exiting... creferhdl.exe
Dear Experts,
I had run DDR4 DATA timing with Hyperlynx (DDRx batch in Boardsim) and SystemSI (Cadence Sigrity).
The result simulation are so different between two software. I detected the reason of this difference below:
In the SystemSI, when I enable package parasitics parameter, the output signals are below:
In the Hyperlynx, per my understanding, R_pin/L_pin/C_pin will be imported to simulation by default.
Note that, my IBIS DDR controller only contain R_pkg/L_pkg/C_pkg and R_pin/L_pin/C_pin, not include [Define Package Model] section.
Can anyone help to understand this difference ?
Thank you so much.
Hi all
I'm drawing the power plan. I have a big shape (principal). Inside a this shape I need to draw other shapes more small. For evry shape i want to have different spacing. (shape to shape). Initially (for principal shape) in the parameters of shape I set (shape/rect) the spacing. In this case all shapes had same clearance. But I want to management the clearances for every shape. How can I get this? Do I have to use the constraint manager?
Thanks.
Hello,
I have an original circuit that I've been soldering up on perfboard with a ton of jumper wires and am getting sick of it taking all day to build 'em. I'd like to transfer the schematic over to a pcb so that I can build them faster and have more standardized production procedures.
I will be using this for commercial devices eventually and I don't want to violate any software license agreements...
A few questions:
Are there any good books or websites that have general guidelines for pcb design?
Is there any software (perhaps free?) that can transfer a schematic directly to a pcb design that only requires a few tweaks to get right?
Has anyone done college coursework or taken other classes in pcb design and would they recommend that route?
What stupid mistakes do people tend to make when they're starting?
Thanks
I didn't find the right solution from the internet.
References:
https://www.muffwiggler.com/forum/viewtopic.php?t=48985
I am trying to create a board outline and would also like to know how once I have created the board outline how to bring it in to associate it with the actual design.
I would like to draw a rectangle shape and then edit the size, is this possible. The manual shows entering in specific coordinates but at this point I would like to draw a rectangle and edit the dimensions once I receive them from my mechanical group.
Once I have the board outline drawn how do you bring this into a design.
Can you create a board outline template and then edit this template to fit your current design.
Thanks
HS
I tried to associate the pspice model for the heterogeneous IC parts in the orcad schematics but getting the error message as the flow is not for the heterogeneous parts only for homogeneous parts. What is the solution for associating the pspice model for the split/heterogeneous parts in the orcad capture.
regards,
Mukilan
Hi,
While discussing with my colleague, he said conductive filling of vias has no impact on current carrying capacity.
When current carrying capacity of vias depends on the plating thickness, why via filling has no effect on current carrying? I think we are increasing the amount of conductor through the barrel. Please explain.
Regards,
Gowthaman
Hello Group,
I am having issue in the last stage of my design. In the *.DLT template from Cadence under folder \share\pcb\text\nclegend. Below note is mentioned.
; Matching of data to a hole is done on the basis of the hole size in field 1 and the plating status in field 2. For a normal hole, the size field is simply '<size>'. For matching to an oval slot hole, size must be '(<major> <minor>)', with <major> being the major dimension of the oval, and <minor> the minor dimension.
In my board file, there are two oval slots with different orientation and both need different custom instruction in the drill table. If I add oval slot info (drill, plating and custom instruction) in the .DLT as per above note, then in the board file, same instruction appears for both oval slot in the drill table while need to be different since orientation is different.
My question is it possible that we can add rotation info of two oval slots in the below line in the *.DLT? Does Cadence support the same? Thanks
((50 40) "Non Plated" "Oval Slot")