Cadence PCB Design Forum

This require a little explanation.
At work we have floating licenses for Allegro HDL, recently upgraded to 17.2.
I generally work on projects from my Windows 7 pc but a colleague uses various Linux computers to access the same projects.
So far everything went (more or less smoothly).

A few months ago I created a new project, including the schematics, exported to PCB and placed the board. When the board was almost ready to go to manufacturing, the colleague decided to optimize some stuff, including replacing some capacitors using the Edit > Global Update > Global Component Change... function.
I think this broke something for me because now I can no longer open the schematics: when I do I immediately get an error window saying

"There was 1 warning while reading XXX.dcf file. See XXX_dcf_read.log for details.

Then the software crashes and I need to close it from task manager.
The content of the log file is

=============================
Problems encountered while reading "P:\cad\designs\XXX\sch_1\XXX.dcf" Read: Wed Feb 14 17:58:07 2018
-----------------------------
Warning: Attribute "CDS_DI_CONTROL_MASK" is not defined. Failed to create "CDS_DI_CONTROL_MASK" attribute for object Design "XXX"

The DCF file is present in the sch_1 folder and I have access (rwx) to it so it is not a permission problem.
I should also mention that I can open the file with no issues from a Linux computer, so it seems to me that there is a problem with a PATH not being defined correctly but, as much as I looked into this, I could not locate the issue.

Can anyone provide some guidance as to what has gone wrong? Any tip on files or paths to check would be really welcome.

Hello,

this is my first post to this Forum. hopefully it is okay?

I use the new new 3D Engine with the Cutting function and it is very importend to add any mirror function for the cutting.

as Sample if you cut the z-axis and you have mounted a hausing at the bottom side then you Need to slide starting from bottom.

Hopyfully i have explaind so you can understand my wisch.

Thanks

Peter

Hi i have some Troubles to map some 3D Step files.

Here a view Samples.community.cadence.com/.../Step.zip

Regards

Peter

I have a mechanical symbol for a #4 hole non plated mounting hole.

After I'm done routing I added them by going to Place > Mechanical Symbol as needed and created the drill chart table. However, I can't see the mechanical holes on the chart, only the holes from vias or components.

How can I add the mechanical mounting holes to the drill chart?

Hi All

I'm generating the artfile \ Gerber for a single layer board.

When I import the created art file to Allegro, All the gerber films are displaying correct except the drill art work which is blank ( only outline is showing).

The details are given below.

Tool - 16.6 version.

Gerber -

Visible layers in drill artwork. -> Board Geometry -> outline and Dimension

Manufacture -> NCDRILL_LEGEND, NCDRILL_FIGURE, PHOTOPLOT_OUTLINE, NCLEGEND1-1, NCLEGEND2-2.

Let me know if I'm missing anything.

PS: On Board file, the drill chart , drill location and dimensions are visible for DRILL_FAB Film.

I have an Allegro PCB Editor file that has a mechanical part that was added but then not used.

But the IPC output refuses to complete because this unused part still exists in the PCB editor file database, even though it is not used. Dbdoctor refuses to remove the part! How can I clean up the Allegro PCB Editor database file to only have used parts stored?

Hello Cadence Community!

I am extensively using automation-generated scripting (*.scr) to automate schematic generation and updating in Allegro Design Entry HDL.

Everything is working well for me, except a quite weird situation:

If I run a piece of script by copying and pasting inside Allegro Design Entry HDL's integrated Command Console, everything is drawn correctly
If I run exactly the same piece of script through the Tools --> Run Script..., instead, the schematic produces an error.

The error I am referring to is the following:

BEFORE RUNNING THE SCRIPT I HAVE THE FOLLOWING:

I USE SCRIPTING TO CONVERT IT INTO THE FOLLOWING:

The lines inside the script are the following:

delete (-5150 4050)
delete (-4850 4050)
wire (-5540 4050) (-4600 4050)
signame (-5520 4050) NEW_SIGNAME__1
paint pink (-5520 4055)
add <ports_lib>ioport (-5590 4050)
mirror (-5590 4050)
delete (-5150 4100)
delete (-4850 4100)
wire (-5540 4100) (-4600 4100)
signame (-5520 4100) NEW_SIGNAME__2
paint pink (-5520 4105)
add <ports_lib>ioport (-5590 4100)
mirror (-5590 4100)

The script does not work well through Tools --> Run Script for the following reason: although cosmetically speaking the result is correct, the errors lies in the fact that one wire gets both netnames associated to it, the other wire gets nothing. To display the issue, here is what happens if I try to move one of the two wires around in the schematic page:

Also, this error happens only to signals/wires/ports that are on the left-side of components (a reuse block in this case) and that closely spaced between each other (50px on the page grid). No overlapping whatsoever, however, happens among wires/netnames/ports.

Any solution to this is greatly appreciated - thank you in advance for your kind contribution!

Paolo

Hello,

I have a question if this is possible: I have an Allegro board file and want to change a few things in the schematic. But I don't have the project or schematic files. Is it possible to create a new project, draw the schematic and then associate my already layouted board file to this project? How should I start? Thanks for your help!

Hello,

I have two .dra files with custom ICs with some pins. Now I am trying to edit this files in Package Designer to move some pins and connected netlist names from one .dra file to the other. After this I want to use this files in my .brd file.

But how can I add a new pin in my .dra file with a netlist name and how can I delete one and remove the netlist connection of this pin from the dra file?

Hi,

I am trying to create a part in OrCAD Capture 17.2, i want to change the grid spacing of the schematic part editor page. I tried to change the grid spacing in "options>>preferences>>grids", it works only with the schematic page. But the part editor page grids remains unchanged. Is there any way i can change the grid spacing while i am creating a library part.

Kindly let me know if it can be done.

Regards,

Chadga

So, i'm rather new to OrCAD & SMD designs, have made a footprint w padstacks for a voltage regulator according to suggestions in data sheet, but not quite sure how i should go about connecting body to ground. It's a two sided board w ground plane, attached picture shows current setup. In the end the connection to ground is not essential, but i'm curious to what be a good approach. I'm using PCB Designer Standard 17.2.

Thanks

Hi sir,

I enable "unused pads supporesion" in inner layers and select "dynamic unused pads suppression".

But there is a error report as below picture.

I check the Constraint rules about HOLE in Constraint Manager . It seems all chart have a constrait rule in constrait manager.

The error shows " not all hole drc ....are enable" . I do not know which one I have not enable.

do you know any methods to solve this?

So, i've got a layout where i want to switch vias globally. Through right click via - modify design padstack - all instances i'm getting a warning "W- WARNING: If this is a via padstack, it must be added to the via list in constraints". However, the via list i get in constrains doesn't correspond to the one in the padstack folder, even though both library and database-parts are selected. I cannot seem to find or alter the location of the "edit via" list in the constraint manager. Any ideas? The attached picture shows the list, and a via i'd be happy to use, if i could find the matching one in the modify padstack list..

Hello. i am new to this whole design process and Cadence. i have came across following errors while i was creating Netlist.

INI File Location:C:\Users\user\AppData\Roaming\SPB_Data\cdssetup\OrCAD_Capture/16.6.0/capture.ini
Could not find \\192.168.5.150\VVDN_CENTRAL_LIB\SCH LIB\SCH_LIB.OLB
ERROR(ORCAP-1169): The Design Cache is integral to the project and cannot be removed from the list of configured libraries.

********************************************************************************
*
* Design Rules Check
*
********************************************************************************
INFO(ORCAP-32002): Netlisting the design
INFO(ORCAP-32004): Design Name:
D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE\5 SWITCH 5 TRIAC AND RELAY.DSN
Netlist Directory:
D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE
Configuration File:
C:\Cadence\SPB_16.6\tools/capture/allegro.cfg

Spawning... "C:\Cadence\SPB_16.6\tools\capture\pstswp.exe" -pst -d "D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE\5 SWITCH 5 TRIAC AND RELAY.DSN" -n "D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE" -c "C:\Cadence\SPB_16.6\tools/capture/allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint" -hpath "HPathForCollision"
#1 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C89: SCHEMATIC1, PAGE3 (4.50, 7.40) .
#2 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C189: SCHEMATIC1, PAGE3 (14.20, 7.90) .
#3 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C233: SCHEMATIC1, PAGE3 (3.50, 7.90) .
#4 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance D3: SCHEMATIC1, PAGE1 (13.90, 5.40) .
#5 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C234: SCHEMATIC1, PAGE3 (2.80, 11.40) .
#6 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R397: SCHEMATIC1, PAGE3 (8.80, 12.90) .
#7 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance
R386: SCHEMATIC1, PAGE3 (3.40, 10.40) .
#8 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance D4: SCHEMATIC1, PAGE1 (15.50, 5.30) .
#9 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C235: SCHEMATIC1, PAGE3 (3.80, 10.90) .
#10 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R387: SCHEMATIC1, PAGE3 (4.10, 10.40) .
#11 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance D5: SCHEMATIC1, PAGE1 (13.90, 6.10) .
#12 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C236: SCHEMATIC1, PAGE3 (14.60, 11.50) .
#13 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R388: SCHEMATIC1, PAGE3 (4.10, 10.60) .
#14 ERROR(ORCAP-36071): Illegal character "White space" found i
n "PCB Footprint" property for component instance R135: SCHEMATIC1, PAGE3 (4.10, 6.90) .
#15 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C237: SCHEMATIC1, PAGE3 (15.60, 11.00) .
#16 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R400: SCHEMATIC1, PAGE3 (9.40, 12.50) .
#17 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R345: SCHEMATIC1, PAGE3 (14.20, 7.30) .
#18 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R136: SCHEMATIC1, PAGE3 (4.80, 6.90) .
#19 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance RL1: SCHEMATIC1, PAGE3 (3.80, 2.20) .
#20 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C238: SCHEMATIC1, PAGE3 (8.80, 13.50) .
#21 ERROR(OR
CAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R401: SCHEMATIC1, PAGE3 (10.10, 12.50) .
#22 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R148: SCHEMATIC1, PAGE3 (15.00, 6.90) .
#23 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance RL2: SCHEMATIC1, PAGE3 (9.80, 2.00) .
#24 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C239: SCHEMATIC1, PAGE3 (9.80, 13.00) .
#25 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R402: SCHEMATIC1, PAGE3 (10.10, 12.70) .
#26 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R149: SCHEMATIC1, PAGE3 (15.70, 6.90) .
#27 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance
R369: SCHEMATIC1, PAGE3 (
3.50, 7.30) .
#28 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance RL3: SCHEMATIC1, PAGE3 (16.00, 2.10) .
#29 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R139: SCHEMATIC1, PAGE3 (4.80, 7.10) .
#30 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance RL4: SCHEMATIC1, PAGE3 (3.90, 4.10) .
#31 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance RL5: SCHEMATIC1, PAGE3 (10.00, 3.80) .
#32 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C92: SCHEMATIC1, PAGE3 (15.40, 7.40) .
#33 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R390: SCHEMATIC1, PAGE3 (14.60, 10.90) .
#34 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property
for component instance R393: SCHEMATIC1, PAGE3 (15.20, 10.50) .
#35 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R151: SCHEMATIC1, PAGE3 (15.70, 7.10) .
#36 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C165: SCHEMATIC1, PAGE1 (6.50, 8.30) .
#37 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R394: SCHEMATIC1, PAGE3 (15.90, 10.50) .
#38 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance R383: SCHEMATIC1, PAGE3 (2.80, 10.80) .
#39 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance D1: SCHEMATIC1, PAGE1 (13.90, 3.90) .
#40 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance C166: SCHEMATIC1, PAGE1 (4.10, 8.00) .
#41 ERROR(ORCAP-36071): Illegal charac
ter "White space" found in "PCB Footprint" property for component instance R395: SCHEMATIC1, PAGE3 (15.90, 10.70) .
#42 ERROR(ORCAP-36071): Illegal character "White space" found in "PCB Footprint" property for component instance D2: SCHEMATIC1, PAGE1 (13.90, 4.60) .
#43 ERROR(ORCAP-36041): Duplicate Pin Name "IP+" found on Package IC_SWITCHER_4 , U26 Pin Number 2: SCHEMATIC1, PAGE4 (5.90, 3.40). Please renumber one of these.
#44 ERROR(ORCAP-36041): Duplicate Pin Name "IP-" found on Package IC_SWITCHER_4 , U26 Pin Number 3: SCHEMATIC1, PAGE4 (5.90, 3.40). Please renumber one of these.
#45 ERROR(ORCAP-36041): Duplicate Pin Name "1" found on Package HDR_2X5_0 , H27 Pin Number 6: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#46 ERROR(ORCAP-36041): Duplicate Pin Name "1" found on Package HDR_2X5_0 , H27 Pin Number 7: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#47 ERROR(ORCAP-36041): Duplicate Pin Name "1" found on Package HDR_2X5_0 , H27 Pin Number 8: SCHEMATIC1, PAGE2 (
4.90, 12.70). Please renumber one of these.
#48 ERROR(ORCAP-36041): Duplicate Pin Name "1" found on Package HDR_2X5_0 , H27 Pin Number 9: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#49 ERROR(ORCAP-36041): Duplicate Pin Name "1" found on Package HDR_2X5_0 , H27 Pin Number 10: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#50 ERROR(ORCAP-36041): Duplicate Pin Name "2" found on Package HDR_2X5_0 , H27 Pin Number 15: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#51 ERROR(ORCAP-36041): Duplicate Pin Name "2" found on Package HDR_2X5_0 , H27 Pin Number 14: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#52 ERROR(ORCAP-36041): Duplicate Pin Name "2" found on Package HDR_2X5_0 , H27 Pin Number 13: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#53 ERROR(ORCAP-36041): Duplicate Pin Name "2" found on Package HDR_2X5_0 , H27 Pin Number 12: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#54 ERROR(ORCAP-36041): Du
plicate Pin Name "2" found
on Package HDR_2X5_0 , H27 Pin Number 11: SCHEMATIC1, PAGE2 (4.90, 12.70). Please renumber one of these.
#55 INFO(ORCAP-36107): PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).

#56 ERROR(ORCAP-36018): Aborting Netlisting... Please correct the above errors and retry.

Exiting... "C:\Cadence\SPB_16.6\tools\capture\pstswp.exe" -pst -d "D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE\5 SWITCH 5 TRIAC AND RELAY.DSN" -n "D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE" -c "C:\Cadence\SPB_16.6\tools/capture/allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint" -hpath "HPathForCollision"
INFO(ORCAP-32005): *** Done ***
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(9.90, 14.10)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(9.30, 14.10)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(12.00, 13.40)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(6.10, 11.40)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(6.40, 8.00)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(6.60, 7.30)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(18.00, 7.30)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(12.50, 12.90)
--------------------------------------------------------------------------------------------------------------------------------------
INFO(ORCAP-2282): The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(18.30, 10.90)
INFO(ORCAP-32002): Netlisting the design
INFO(ORCAP-32004): Design Name:
D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE\5 SWITCH 5 TRIAC AND RELAY.DSN
Netlist Directory:
D:\DESIGN\5 SWITCH 5 TRIAC ORCAD FILE
Configuration File:
C:\Cadence\SPB_16.6\tools/capture/allegro.cfg

#19 ERROR(ORCAP-36018): Aborting Netlisting... Please correct the above errors and retry.

I think i have made a silly mistake somewhere in the design that's why i can not find this "illegal character" and "Duplicate pin no." error. I have tried to change PCB FootPrint of each component but it doesn't work. it still show me same set of errors.

Please help.

Thank you in advance

Hi,

I watched this video so I know it is possible to bend areas of the PCB in the 3D canvas viewer.

https://www.youtube.com/watch?v=trmPd_7_8yQ

When I right click on the canvas or flex area there is only a greyed out option for a bend. I thought it might be I didn't have a bend zone but I added one and still the option is greyed out. I've attached the bend.brd PCB file that I am trying to do a basic bend.

Thanks for any help!

community.cadence.com/.../bend.zip

Hi,

In the schematic, I use the code below for Ref Des Pattern to assign refdes according to their corresponding page numbers.

($PHYS_DES_PREFIX)($PHYS_PAGE)[0-9](01) or

($PHYS_DES_PREFIX)($PAGE)[0-9](01) - i don't know the difference to be honest but they both work.

I am not sure if that's a correct approach but it usually works. There is one exception. If I copy or cut some components from another page and paste them to a new page, with this code, sometimes the refdes is assigned with their previous page numbers but not with their current one. How can I fix this?

thanks

Reduce blank page borders in exported PDF from OrCAD Capture

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Drill_Fab Artwork \ Gerber is Blank

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Grid spacing in schematic part editor

Connecting component body to ground on smd board

When I enable "unused pads suppression" Error Report: Not all hole DRC....

Location of "edit via" list from constraint manager

Illegal Character and Duplicate Pin Name

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