I have two almost identical bend zones setup in my PCB file. The only difference is one has the top as the inner side and the other the bottom to create a "stacked" PCB. The problem is 3D Canvas viewer doesn't seem to accurately show the bend radius or length. See that attached BRD file and image that shows the issue.
community.cadence.com/.../pcb.zip
Using 17.2 SO35. Routing a board that has a CPU, CPLD and SD ram. Did an earlier board at an earlier revision (17.2 not sure what version) that had the same combo with Address and Data lines going to a T and then split off to the Ram and CPLD. This was done by removing one segment of the trace and then measuring from the Via to get the overall length of that segment (CPU to CPLD).
Then removed a segment of that trace and put the other one back. Then was able to tune the length of the last segment (CPU to SD Ram) to match the length of the first measured segment (CPU to CPLD). In the latest version even if I remove one segment of the trace when I measure from the via it high-lights the whole net and gives me the length of the entire net including the section that is disconnected. I know other people are doing this same thing with a CPU, Ram and a CPLD.
What method are you using to do this?
Are there industry-standard guidelines for naming footprints which are otherwise similar but have different pins missing? For example, take a look at the package options at http://www.onsemi.com/pub/Collateral/NCP1076A-D.PDF. They are both like an 8 pin DIP, but either pin 3 or pin 6 is removed.
IPC-7351 covers Hidden Pins and Deleted Pins, but I don't see any guidelines for this specific case. They would both be DIP-7-8N if I read the IPC doc correctly.
Has anyone encountered this before? And, importantly, has a good solution? Certainly there are a lot of ways to add suffixes or some other variation of the footprint name to differentiate these footprints, but I'd rather get some experience of what works instead of realizing later whatever I came up with was a mistake.
Hi,
I tried importing the IBIS model into model editor by selecting the IBIS model. once I select the IBIS file and click on OK. I get the following error as shown in attachment do help me resolve the issue.
Hi Folks,
Anyone use the new feature which allow you to define the counter bore/sink in the Padstack editor?
Right now it is allowing you to define it from Top side but if i need it to define from bottom side, then what i need to do?
Thanks
Khurram
I have written some nice reports for internal use, both text reports and HTML reports. Both displayed fine in 16.6.
In 17.2, my text reports are still OK but the HTML reports just display the raw HTML text instead of being formatted and displaying as an HTML page. The Allegro SKILL 17.2 manual, page 1272, still mentions both types of reports being available. The included Allegro reports that are HTML format still work OK, so it’s something about my custom HTML reports.
I looked on COS and the PCB Design forum and didn’t see anything. Neither does $CDSROOT\share\pcb\examples\skill have anything about this that I can find. Then I searched for “html” in User Prefs and found a couple variables. Unchecking “allegro_html_qt” makes the reports display properly. Now knowing this, I found a few entries on COS that sounds like the HTML viewer has changed in 17.2 from OpenGL to Qt. Perhaps that’s the issue?
Has anybody else run into this issue? What fixes it? Or alternatively, if you have a custom HTML report working in 17.2 with the allegro_html_qt variable checked, how is your report formatted?
Here is the displayed text from an example board I made with allegro_html_qt checked. This is exactly what is displayed in the report window; Allegro does not understand this is HTML and should be displayed as such:
<html><b><u>Design name</u> C:/DATA/Projects/Cadence/test/comp_lead_prep/worklib/comp_lead_prep/physical/comp_lead_prep166.brd<br><u>Date</u> Mon Mar 12 16:11:00 2018</b><br><br><table border="1"><caption><b><u>QSC Component Lead Prep Report</u></b></caption><tr><th>Ref Des</th><th>Part Number</th><th>Footprint Name</th><th>Tooling</th><th>Lead Prep Doc</th></tr><tr><td>Q1</td><td>QD-000373-00</td><td>Q_MFN_TO220FLUP150</td><td>B3</td><td>RD-000487-00</td></tr><tr><td>Q3</td><td>QD-000284-00</td><td>Q_MFN_TO247FLUP220</td><td>C</td><td>RD-000488-00</td></tr><tr><td>Q4</td><td>QD-000284-00</td><td>Q_MFN_TO247PRPC</td><td>ND1</td><td>RD-000042-00</td></tr></html>Hi all,
I have a simple design in DEHDL using an old component that has a hidden ground pin (no supply, it's an octal transistor with a common ground). The message is:
WARNING (thc_pin_masqued)
Implicit PowerPins on instance
Instance : i170(1)
GND
I've checked that the ground pin has been allocated to the correct signal, can anyone tell me what causes this message?
best regards
George
I can successfully import my PADS layout into PCB Editor with the exception of any 2D drawings that are on the silk layers (i.e., logos, arrows. plus/minus signs, etc.). I can see these elements in my PADS library, but they are only identified as 2D Lines, which the Allegro Library translator does not support (it seems to only import parts and decals from a PADS library).
Is there any way to import these 2D line drawings from PADS? This would be a lot of work to recreate, since the original drawing files were lost in a drive failure several years ago.
So, i've had PCB Designer Standard crash on me 4 times over the past few weeks. After the crash i cannot use the program, as the license isn't released. The first time i could "Reset licence cache", but now the option disappears after clicking the button. I also don't have access to the server, as this obviously only happens after system admins have left.
Can i manually release the licence?
In our products we would like to be able to select interchangeable parts. Let me discuss quickly why this is useful and our motivation. We may want to allow purchasing of two parts for lead time (availability) or cost reasons. Or we may manufacture a product in different locations with one part number preferred at one location and vice versa, but both part numbers are acceptable. The reason to have two unique part numbers is that the parts may not be interchangeable in all designs, so on a design-by-design basis the interchangeability must be determined. Therefore, one part number cannot have multiple manufacturer part numbers.
Here is a concrete example of how this could work. At location Q45 there may be two different transistors that can be used. Each transistor has a unique part number and the BOM should show that either part number can be placed at location Q45. Some method of allowing multiple part numbers for one location must be provided.
Is there an existing way to do this within the DEHDL - Allegro flow?
I have used the word "interchangeable" above instead of "alternate" to avoid any confusion with the Alternates feature of Variant Editor. I know how to use Alternates in Variant Editor and that is not what I want.
How do I add text to the RefDes->Silkscreen Top or Bottom layers without attaching it to a component?
For instance I want to put a label on the board and then change it later, but if I assign it to some random component, changing the text later then causes that component's label to change as well.
Is there a best practice here? I want to be able to label my board but not have to add dummy components for every new piece of text I add.
Thanks,
David
Hi
Why some step 3d models are displayed in pink colour 3d canvas?
Regards
Kriss
Hello I have these Unrouted connections. These are all the 0 (or gnd) pin of various components an I will connect all these to the Ground (I will have a ground plane - Dynamic copper on the top).
Is there any actual problem occurring from this situation? I mean, I intend to ignore these warnings. Will the final gerber files have any malfunctioning? Will this affect production?
Also I did not find anything relative to this in the Documentation - maybe I did not search deep enough, any point where I should look?
-> Allegro ver.17.2
Thanks alot!
Regards,
Andreas
Hi,
I am using OrCAD Pspice Plus 17.2 version. In smoke analysis, i want to assign one derating factor for a set of resistors and another derating factor for the rest of the resistors. How can this be done.
When i go to create a custom derating file, i can provide derating values globally for a resistor. I want to assign different individual values for each component.
Kindly help me on this issue.
Regards,
Chadga
Hi,
I am using OrCAD pspice plus version 17.2, and am working on a design where i have to provide a load profile.
Ex: My input source is 28V DC supply. initially my load will have some voltage across it. After 1 minute i want my load to draw only 5V and later after 3 minutes it should draw 10V.
Is there any way where i can provide a profile in this manner.
Kindly help me on this issue.
Regards,
Chadga
Hello,
Is there any way to fix a page border in position in Concept HDL 17.2 ?
During schematic entry the tool often selects the border (when clicking near it) and drags it all over the place which is pretty annoying.
It can be locked by right click -> lock. But it must be done on each page and then the properties cannot be edited anymore.
It would be nicer to arrange that with a property which can be placed on the symbol in the library or option in the tool.
Any ideas anyone ?
So i've run into a bit of a rut. I renamed some connections in Capture, the hierarchical block had to be replaced, whereas netlist generation was impossible because of duplicate refdes for all parts in the block (although there was only one in the design and no actual duplicate parts?). As i saved a copy to edit, i had the wrong project file selected as i did an annotation and now i have a hard time back annotating or redoing the list without placing all the components over.
Is there any way to clean up this mess in an orderly way? Or manually edit the small details needed in the netlist? PCB editor 17.2
Thanks
Last year I had gone thru the library and updated all the footprints and pad stacks to 16.6 from previous versions of Allegro.
I was able to multiple files at the same time. Unfortunately I do not recall how i had done it at the time and do not see anything similar in the posts.
Does any one know how to do this on multiple parts at the same time?
Basically i want to convert them all from 16.6 to 17.2
Hi all,
I've been using CIS for some years now, and it's *great* when set up to query a MariaDB running on linux. (Upwards of 500k parts in the database, but database query is pretty quick).
One thing bugs me though: if I "browse" the database, I can set the appropriate columns, and they'll be saved for the next time I browse that particular database table. But if I "query", then it doesn't matter which table I'm querying, I'll get whatever columns were set up from the last query, even if it was a different table.
Which looks like the "CIS query columns" are set up in capture.ini, and are global for all queries (again, Browsing has per-table setup, so not a problem).
(For example, query in the 'Resistor' table would have things like 'tolerance' and 'tempco'....which are irrelevant for querying the 'BJT' table, while the VCE property should be visible for querying the 'BJT' table but hidden for the 'Resistor' table)
So first a question: is there some way to set up queries so that they'll switch column visiblity, based on the table being queried? (my guess, is NO)
And if not, a feature request: either provide per-table column visibility configuation (just use the 'browse' definitions?) in a file, or provide capability so that the databases can provide the information about which columns should be displayed/hidden.
Does anyone have a way to change a Ref Des for a part in Capture and not have it impact the part in Layout?
Typically when a Ref Des is changed the part is removed from the layout but we'd like to keep the circuit intact and just rename it following our page numbering sequencing.
Sheet 1 = 100 to 199, Sheet 2 = 200 to 299 etc.
Any comments would be helpful.
Thanks