I have done some test and seems that Pad Translator loose any swappability info of the components.
It generate always 1 gate containing all the pins.
Also all the pins are NOT swappable.
the same appens from the translation from ALTIUM.
Is there a way to receive the correct device.dev. ????
Also when i try to translate the PADS Library the translator loose all the Gate definitions inside the filename.p
Any suggest?
Is there an automated method (not manual) for controlling the page ordering in a schematic design with a complex hierarchy? Manual editing will only cause problems as pages are added and deleted.
For instance a schematic may have individual DRAM channels (A,B...) connected to multiple DIMMs which are located in hierarchical blocks. For each DRAM channel all connection to the hierarchical blocks are contained within a single page of the root schematic. The next page of root contains a different channel with different DIMMs. Currently the annotator appears to process all pages in the root schematic before processing the various hierarchical blocks which then appear in random orders once annotated. As an example, Channel A may be first in the root schematic but the DIMMs that are connected to channel A appear after the DIMMs for channel B once annotated (see below)
page 1 Channel A
page 2 Channel B
page 3 Channel A DIMM 2
page 4 Channel B DIMM 1
page 5 Channel A DIMM 1
page 6 Channel B DIMM 2
It would be optimal for readability if the ordering could be controlled. In this example having the various DIMM pages be in sequential order directly after the page in which they are referenced by the hierarchical block seems to make the most sense (see below).
page 1 Channel A
page 2 Channel A DIMM 1
page 3 Channel A DIMM 2
page 4 Channel B
page 5 Channel B DIMM 1
page 6 Channel B DIMM 2
Hello Group,
I really had a hard time to identify formula through which Allegro is calculating via delay (z-axis delay) from propagation velocity factor.
In CM, default value for propagation velocity factor is set as 1.524 e +008 = 1.52400000000 while in cross section, I used FR-4 with 4.5 di-electric constant (default values for FR-4 from Cadence database)
In Allegro, via length is 1000 mil. From ECS, via delay came out to be as 0.16667 ns (I already subtracted trace delay from total delay of trace & via). However for 1000 mil trace length, it shows delay as 0.1738 ns
I have below questions.
1) How this value 0.16667 ns (via delay) is calculated based on 1 inch via length with factor 1.524 e +008 ? As per pdf documentation, this velocity factor is used to convert units (from length to time) but not sure how.
2) Why delay is different between 1 inch via length and 1 inch trace length?
3) Can I say that via delay does not depends on Allegro cross section settings, rather just on propagation velocity factor?
4) Do we need to change this propagation velocity factor based on dielectric material in cross section?
Sorry for many questions and appreciate if some one could shed light on the same.
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases,
but strangely i can see the possibility to see my cases already sended.!!!!!???????).
Also i need to know how is possible send enhancements request for new features.
any reply will be appreciated.
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases,
but strangely i can see the possibility to see my cases already sended.!!!!!???????).
Also i need to know how it is possible send enhancements request for new features.
any reply will be appreciated.
What I'm trying to do...
I need to simulate two NMOS transistors each with custom parameters. I would like to have my own Library in which I can build individual non-associated (meaning: if I change the modal name and parameters for one it only applies to that model), custom parts that have functionality and can be used in the same schematic. I've been trying for two days now and have read many articles, but still I don't clearly understand what's going on with all the different file types and there functionality in the different programs (ie: lite/student versions of Pspice, Capture, Pspice-Model editor).
What I've tried to do so far...
In Capture I add a part to the screen. Then, I select, right click the part and "Edit Pspice Model".. Then, in Model Editor I try to change the Model Name and a one off "part" the that will be the same king of device in my Schematics but with different parameters and a different model name. I've also tried to open Model Editor on it's own and make a library and add parts but it doesn't recognize the .OLB Breakout files.
What I don't Know...
I don't know what the difference is between the file types (.LIB .OLB .MOD .OBJ) and I don't understand the association in models and libraries and (you name it). I understand that there maybe can also be different models based on locality, meaning simulation profile specific vs global library vs Schematic and such.
RESTATED. I just want individual N-Channel MOSFETs on the same schematic in Capture, Whose properties can be different (ie LAMBDA, VTO, W, L, ETC.) AND Whose names can be different.
Thank you in advance, to anyone that can help.
Hello,
To Create PQ and EFD family type transformer in magnetic part editor?
Is there any way in data entry to provide PQ and EFD Family As well?
regards,
jishu
What is the recommended method of defining generic microvia padstack in PCB Editor 17.2?
My attempt was making a regular via padstack with all layers defined. Then go to Setup > BB via Definitions > Define BB Via and map the start/end layers. However this method doesn't remove layers on either side of the via and the via goes all the way through the PCB.
*Surely* you don't have to make an individual padstack that goes from layers 1-2 and 2-3 for example: v10h5_1-2.pad and v10h5_2-3.pad. That would be cumbersome.
Dear All,
I have a shape made of dynamic copper on TOP. There is a net assigned to it (RL), as you can see
When I stretch it it loses the connectivity, becomes unfilled
and gives error in status:
Dynamic shapes out of date: 1 out of 15
Current fill mode : SMOOTH<<< ETCH >>> Layer = TOPState: No Etch Point on shape: (-1.808 1.376) Net: RL
How to solve this?
Thanks
Francesco
Ok, I'm stuck......
I have a 144 pin 0.5 pitch BGA that I want to make a footprint which includes the fanout. Signals will use a blind via from the top layer to the second inner layer. Power pins will use a standard thru via. I have both padstacks created, the thru defined on all layers and the blind defined on the top and second inner layer (I have the default internal set to null). Both vias are specified in CM Physical Constraint Set and show properly in the cross section view there.
When I bring the footprint into PCB Editor the blind padstack is now defined on every layer. I have to go into the edit padstack tool and set the unused layers to null in order to get the blind via back that I had specified when I generated the footprint.
I am obviously doing something wrong. I have searched the web, read many things and watched a couple videos but don't seem to be able to find the solution.Obviously I'm doing something wrong . I want a BGA fan out that uses a combination of blind and thru vias designed as a library part that can be brought into PCB Editor and used without further editing. Thoughts?
Tom
PS: Using ver 16.6 Pro
I am able to open CIS explorer to see folders which were pulled from from My Access Database but I have the following errors that appear:
ODBC Error Description: State:07001,Native:-3010,Origin:[Microsoft][ODBC Microsoft Access Driver]
ERROR(ORCIS-6245): Database Operation Failed
Please Check Session For More Details
ERROR(ORCIS-6250): ODBC Error Code: -1
Description: Too few parameters. Expected 2.
Both the 6245 one as well as 6250 one appears when I move from one Access table to the next in CIS explorer. No information appears when I try to show part information which is supposed to be contained in the relevant folder.
I'm not sure if the reason these errors are coming up are due to Drivers or a a corrupt ODBC datasource or if they are Bad column Names in the Microsoft Access file for some of my different tables?
Could be any number of things.
The database name was "COTS Database" shown added as an ODBC datasource in screen 2.
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Hi, I am having some trouble with my CIS database in Orcad. After opening the CIS Explorer and then click on a part I get the error below. After clicking OK in the dialog box I am able to place the part and everything looks ok. But the dialog box pops up each time I click on a part in CIS Explorer.
We are using CIP-E. I get the impression that this occured after I was changing the database views in CIP-E web interface.
Dialog box error:
Error(ORCIS-6245): Database Operation Failed
Please check Session for more details
Session log details:
ODBC Error Description: State:37000,Native:156,Origin:[Microsoft][ODBC SQL Server Driver][SQL Server]
State:37000,Native:8180,Origin:[Microsoft][ODBC SQL Server Driver][SQL Server]
ERROR(ORCIS-6245): Database Operation Failed
Please Check Session For More Details
ERROR(ORCIS-6250): ODBC Error Code: -1
Description: Incorrect syntax near the keyword 'WHERE'.
Statement(s) could not be prepared.
I found this on web, but can't really relate it to Orcad/CIS etc.
support.microsoft.com/.../statement-s-could-not-be-prepared-sql-error-37000
Hi,
Is it possible to turn off via mering?
For example I have a 12 layer board. If I place a via from 5:7 and place one from 7:9 on it, it merges them together to 5:9. I don't want them to merge, so I can move both via's on their own.
I've tried changing the Pad-Pad Connect setting, but it won't change anything. THe via's are still merging.
Using:
Regards,
Michiel
Hi all
I'm trying to understand the netlist file generated by Orcad capture. see screenshot
what does "I505679590" define and how can i find it of other components?
many thanks
We are attempting to justify buying the High Speed Option for Allegro 17.2. I can find the lists of improved functionality, but I need to write up a presentation that states in layman's terms what we can accomplish with the High Speed Option that we cannot do today. Our layouts currently contain high speed buses and Gen 4 DDR. Can some of you tell me what your favorite part of the High Speed option is that you could not do before? Thank you for any feedback you can provide.
Is there an "automated" way to match trace lengths (defined in a match group) other then setting the longest trace as the "target" and then using the manual slide tune tool to bring all of the traces in the group into tolerance?
Tom
When routing a differential pair and transitioning to another layer, the via spacing is wider then I would expect.
For example, I have the diff pair trace to trace spacing set for 0.3mm but the vias are being spaced 1mm apart. I have the via to via spacing set to much less then that in CM.
Where should I look for a setting that controls the via to via spacing on a diff pair?
Tom
PS Using 16.6 S102
Hi,
I'd like to extract all the nets that is routed in a specific are on PCB on each layer. For example I have a component U10, and I'd like to see all the nets routed around it that is max 5mm away.
Is there any way to do it quickly?
thanks,
Hi,
Is there any easy way to define an area of pcb, then removing anything else outside of that area? But the routed signals, components etc won't change inside of the area?
Hi all,
I'm looking for a easy way to calculate tracks resistance about my board. I have compiled the cross section with thickness. Is possible get the resistance in DC/frequency about specific tracks? For example to click on tracks?