when you turn on a layer in the visibility tab and turn it off the shape boundaries do not turn off. This is annoying. Is there some way to stop this? I don't want to see the dynamic shape boundaries unless I am editing the boundaries.
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is there anyway to prevent Allegro from displaying boundary for shapes?
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DRC checks mechanical clearance
I'm looking for a way to create keepouts for specific nets. Actually a keepout for every net except "GND" (return). Our current process involves importing mechanical housings/isolation covers into Allegro (dxf) and manually reviewing for minimum clearances. This is not a very good process. The attached image shows the isolation walls(red) and soldermask (violet). The image is a small fraction of the area that we need to verify.
Needless to say, on occasion we've missed a spot or two.
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Funckey and Alias in Env file work erratically in latest Hot Patch
Hi, is any one else going crazy with funckey call outs while in Allegro? Ever since 17.2 HP 032 Cadence has done something that most of my funckey stop working.
E.g. I use a Macro keyboard with all of the keyboard keys mapped to it. I start a route with a key on the keyboard then complete the route with another key on the keyboard which is mapped to end.
It seems to work for a little bit and then suddenly it won't do anything. I can't complete my route by hitting the end key. Seems if I right click the mouse and go back to the canvas the macro keyboard starts working.
If I have to right click the mouse I might as well hit the end on the popup instead! Defeats the purpose of a macro keyboard!!
I've had tech support look into it but they asked to change all of my alias to funckey commands instead but that didn't work. I've rolled back to HP 030 twice now.
Here is what my Env looks like.
alias F5 replay LibrarySetup
alias F6 replay Package_height
alias F7 replay Padstack_replace
alias F8 replay Padstack_edit
alias F9 replay view_routing
alias F10 replay view_bottom
alias F11 replay view_top
alias F12 replay view_top-bot
funckey Pgup zoom in
funckey Pgdown zoom out
funckey Home zoom fit
funckey Del delete
funckey Esc cancel
funckey Insert next
funckey f 'settoggle gridvalue 0.1 0.01; replay set-grid $gridvalue;echo grid = $gridvalue'
funckey F 'settoggle gridvalue 0.1 0.01; replay set-grid $gridvalue;echo grid = $gridvalue'
funckey g 'settoggle gridvalue 1 5; replay set-grid $gridvalue;echo grid = $gridvalue'
funckey G 'settoggle gridvalue 1 5; replay set-grid $gridvalue;echo grid = $gridvalue'
funckey m 'settoggle gridvalue 3.937 15.748 19.685; replay set-grid $gridvalue;echo grid = $gridvalue'
funckey M 'settoggle gridvalue 3.937 15.748 19.685; replay set-grid $gridvalue;echo grid = $gridvalue'
funckey 0 replay slide
funckey 1 "add connect"
funckey 2 replay find_groups
funckey * toggle
funckey End Done
funckey / "pop neck"
funckey 3 replay full_contact
funckey 4 move
funckey 5 iangle 90
funckey 6 "prepopup;pop mirror"
funckey 7 replay find_symbol
funckey 8 replay find_trace_via
funckey 9 replay find_net
funckey w 'settoggle minw 10 12 15; setwindow form.mini; FORM mini acon_line_width $minw; setwindow pcb'
funckey s "Spin;iangle 45"
funckey S "Spin;iangle 90"
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Blind Via Stackup
I think I may have painted myself into a via corner........
Working on a blind via board - I don't do this very often so bear with me - it is an 8 layer board with a few 144 pin 0.5mm pitch BGA's. Directly below these BGA's are a couple high fine pitch 168 pin connectors. Oh and throw in some diff pairs and 50 ohm RGB video signals.
Instructed to use blind vias - no buried.
Stackup:
Layer 1 - signal
Layer 2 - gnd
Layer 3 - signal
Layer 4 - pwr
Layer 5 - pwr
Layer 6 - signal
Layer 7 - gnd
Layer 8 - signal
I worked with the board house to come up with the layer to layer and trace width spacing to meet the diff and impedance requirements.
I have structured the blind vias as follows:
L1 to L2 to pick up gnd
L1 to L3 to get first inner row of BGA to signal layer
L1 to L4 to pick up power
L1 to L5 to pick up other power (board has several powers 1.8, 2.5, 3.3, 5 and 12v)
L1 to L6 to fan out inner BGA pins
Then from the bottom up
L8 to L7
L8 to L6 connector pins to signal
L8 to L5 connector to power
L8 to L4 connector to power
L8 to L3 connector to signal
Then the standard thru via used for many other non-BGA area signals
After reviewing this and thinking about it a bit I believe that my L1 to L3, L1 to L5, L8 to L6 and L8 to L4 vias (which are the most utilized) are not manufacturable since they end up on the top surface of an inner layer. Am I correct in this thinking? I have a call into the board house to ask them but have not received a reply yet.
One option is to convert the L1 to L3 to L1 to L4 and suppress the unused pad on L4. Same with the L8 to L6 - convert it to L8 to L5 and suppress the unused pad on L5.
Am I mixed up or ........... Need some expert input.
Thank you.
Tom
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Cadence Allegro UI 17.2 "productivity decrease" vs 16.6
Hi guys, there are some nice features in Allegro/Orcad 17.2 vs 16.6 but OMG the user interface is like "Killing me" in 17.2.
Couple of examples:
In 16.6 the "Visibility, Options & Find" windows collapse nicely on the right hand side of the screen. Hovering over these menus in 16.6 allows them to pop out. That's kind of neat in that allows fast access to those menus without a click. Simple hover make a change done, works good.
In 17.2 those menus require a click to invoke them and collapse them. No mouse hover invokes them sliding out. Does anyone know what prompted the change in this lack of functionality vs the prior version ?
In 17.2 there is some high strangeness with the options panel popping out. For example if I click on the grid to toggle it on and off, Bam out pops the options panel. If I click on the add a connect, place a cline then select done again the options panel pops out. If I click the constraint manager to invoke it yep you guessed it the options panel pops out yet again. It has become really annoying. I'm sure there are more
than what I have just mentioned.
In 17.2 the Constraint manager is more difficult to navigate. The right hand pane where you set the constraints is not logical. In 16.6 they have tabs at the bottom so you can easily see it your setting spacing rules such as Line-To, Shape to etc.
Can anyone offer any insight, in particular with respect to that "Options Panel popping out" , Does it do the same thing on your end if it is collapsed ?, It would be great to restore former functionality to 16.6 via a user setting switch in 17.2
I am running 17.2 s038 latest cut on win 10 but due to the annoyances mainly use 16.6 on win server.
Thanks
Paul.
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cis db error
very oftern i get the error orcis-6245:Database operation failed when i try to place components through CIS in ver17.2. we have upgraded the ODBC to 64bit and the placement of components works fine if database sits in local PC. But with database sitting on server i get this error(across users) and this happens not all time but few instances. To solve this i again map the dbc file to fix this. Any permanent solution for this?
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Trace length matching
I have three traces that need to be matched within a certain percent. ONE of these traces has a resistor inline. How do I combine the two nets that comprise the signal trace into something that CM can calculate the trace lengths and add them together for comparison to the other two? I have tried combining them into a net group and adding that to the match group but that doesn't seem to work.
I only have two traces to do this to and can easily just use the old calculator and add the two lengths together, but I thought there might be another way to have it calculated automatically.
Ver 16.6 latest SP
Thanks,
Tom
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Bottom soldermask Gerber Problem
I am having difficulty with the bottom soldermask gerber file in a 2 layer PCB in which all components are located on the top layer. There are no holes or any other features on the bottom side, so essentially the bottom soldermask gerber file should be blank. The bottom soldermask gerber file is generated by OrCAD, but when I try to open it in a gerberviewer, the file type is not recognized. Further, the PCB manufacture we sent the board to is having trouble with it as well. They had to ask us if there was soldermask on the bottom layer or if it was unmasked altogether. I'm curious if there is a work around for this situation and any help is greatly appreciated.
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Constraint region overrides net based constraints
Using 17.2 I have created a rigid-flex PCB. By default when a zone is created PCB Editor creates a constraint region around the perimeter of this zone. This is fine except when the nets within this zone require net based spacing requirements. PCB Editor seems to prioritize the constraint region over the net based constraints which ends up violating net spacing rules but no DRC is created. Is this normal? Is there a way of setting the priority of the spacing constraints?
Thanks!
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Using Variants in MCAD Export
I would like to export 3D step files according to variants.
Is there any possibility to do so?
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Export .BRD to ASCII. ALG
Hi,
as the headline indicates im looking for infomation on how to export the *.BRD files into ASCII .ALG file. Why im seeking this - because of an export tutorial in Altium that refers to this ASCII file trick *.ALG.
Been googling for some time now and looking in the OrCAD help for clues on where this export function is located, apparently with no luck.
Im normally running Altium 17 / 18. However now trying the OrCAD trial due to the fact that more customers have this as inhouse Tool. As Altium is main CAD program I'd like to see the OrCAD to Altium Export Work.
Thank you in advance for any help or clues.
Maybe it's a Unicorn?
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Changing Axis for Dimension
Typically use linear dimensions. This time I want to specify some features and want to use datum dimensions. I can get the dimensions in the X Axis direction - but can not get any in the Y Axis. Seems to be stuck on the X Axis and I can't figure out how to switch between axis. Tried RMB - no option, looked thru dimension environment parameters - no help there either.
What am I missing?
Tom
Ver Pro 16.6 latest SP
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TCL command for "Tools > Export Properties.."
I'm looking to automate the export of part properties from OLB files. Does anyone know if there is a TCL command/function that can use export part properties? This generates an EXP file that I am going to use for revision control of the OLB files.
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Unable to access OrCAD 17.2 software in User login
Hello,
I m using OrCAD 17.2 version and the it is working fine in admin login but, when I try to open the software in user login the tool enters into lite mode and doesn't open in licensed mode.
Kindly help me resolve this.
Thanks,
Shiv
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How to remove/ delete the pre-existing home path and point it to new location
Hello,
I have installed OrCAD 17.2 in C drive later I uninstalled it and re-installed in D drive but the home path isn't getting updated.
The home path is getting pointed to previous home path location when the tool is opened.
In computer >> properties >> advanced system settings >> environmental variables the home path is pointed to new location but when the tool is opened it picks the home path from the previous path location
Kindly help me resolve this.
Thanks,
Shiv
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Cant see the complete window of Quick place
Hi,
I am using orcad pcb 17.2 version and i have the latest update(hotfix 38). But when i go to quick place in PCB editor, i wont be able to see the Ok ,Cancel and Apply buttons.
i tried changing my display resolution and none of it helps. Is there any other solution to this issue.
i have attached the screenshot for more information.
Kindly help me on this issue
Chadga
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Allegro 17.5 Padstacks - Rounded rectangle for IPC SMD Footprints - Corner radius value recommendation ?
In 17.5 there is the option to do rounded rectangles which is great. I have been thinking of updating my standard IPC-7351 resistors - caps etc to use the new rounded rectangle pads as opposed to the traditional rectangular ones.
Can anyone offer any guidance with respect to a good rule of thumb to apply to the "Corner Radius Value" I'm thinking 5 but not too sure.
Thanks
Paul
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Accel(Shortcut) In RegisterAction Not Work In Orcad Capture 17.2
I want to create an shortcut for my tcl script (for exmaple Tcl1) so when I press "Ctrl+Shift+M" orcad run my script. To do that after reading many pages I reached to the following code
proc Tcl1 {} {
capDisplayMessageBox "This is a test" "Tcl1"
}
RegisterAction "Tcl1 Label" "capTrue" "Ctrl+Shift+M" "Tcl1" "Schematic"This will create the shortcut but the created shortcut available only in the schematic window. I want to able to run this script anywhere (like in Symbol Editor) so as documentation and examples suggested I removed schematic in the last argument and execute following command instead
RegisterAction "Tcl1 Label" "capTrue" "Ctrl+Shift+M" "Tcl1" ""
But in the new case the command hitting shortcut/accel wong trig script anymore although the action is registed (confirmed by running UnregisterAction). Please if you know how can I solve this issue comment down below
Thanks
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how to open a .brd file in capture
Hi all
Is there a direct way to open .brd file in capture or i need to export it as something else? I'm using 17.2
Regards
Z.
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Disable v17.2 Start Page
Hi,
I just updated from OrCAD PCB Editor v17.2 S001 to v17.2 S038. According to the documentation, the new Start Page was added in S031. How can I turn this off? I know how to do it in Capture, but can't find out how to do it in PCB Editor.
Thanks.
--Mark
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