Is there an option to prevent a trace from connecting to shape of the same net? For instance, I would like to route a GND trace directly to the decoupling capacitor pad through a ground plane on the same layer. Then connect to an internal ground plane through another trace from the same pad.
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Prevent routing to shape on select nets
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Generated .mkr file instead of .psm
I tried to checked-in my footprint to the database but the error says that no .psm file was found in the folder. When I checked my folder, it contains .mkr.
Been doing footprint for a while and used script to set-up my working environment. This means that I have not change any of my settings.
I created a new one, the same error pops up.
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CIP error when adding a new part
Hi
I encounter this error several times whenever i try to add a new schematic part from online distributor search in my library.
The problem is that i have never added this part before in library but still it says it has been added.
Thanks
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[Orcad PCB] Drag / slide shapes made out of lines
Hello
We would like to expand the sides of a silkscreen rectangle we have drawn using the line tool.
One way of solving it seems to be to move the line segment, then right clicking the endpoints of the now remaining, disconnected lines and select "move vertex". How can we drag or slide any line-shape without too much clicking?
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Autoroute in 17.2? and a few other orcad related questions.
Hey guys, haven't posted in a couple of weeks, so things are obviously going a bit better(Thanks to you folks), but I have run into some issues that I'd like to ask about.
1.) Does orcad 17.2 have autoroute? I am having a nightmare of a time with a new microsd connector that has a different footprint than our last one. I made a new footprint, but i'm having trouble finding a path for my traces. Just out of curiosity I thought i'd like to try autoroute, and see if it helps even with 1 or 2 connections, but unfortunately I can't seem to find it in 17.2. Is autoroute in 17.2? has it been replaced with something else?
2.) Randomly, 'place via' is now greyed out, and I can't seem to add via's anymore unless I copy and paste one in.
3.) I'm running into all sorts of DRC errors, but some of them existed before the file was past on to me. Obviously, no drc errors would be ideal, but are they sometimes ok? Obviously, not all DRC errors are created equal, and are based on rules put in place by the previous designer, but can I leave some of them in place? Some of them seem unfixable (at the moment, with my current skill level).
4) How do I avoid 'Differential pair phase tolerance'. I've run into 4 on the current board, and I can't seem to figure out how to fix that issue.
5) Is there a step that I can do at the end to check the integrity of the board before I send it off for prototype?
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Constraint Manager Analysis Error (Allegro PCB Designer 17.2)
I have created a set of constraints for differential pairs in the 'Electrical Constraint Set', and established several sets of differential pairs. Whenever I right click and Analyze a set of differential pairs the boxes I am expecting to fill with 'Actual lengths' and 'Margin' for 'Uncoupled Length' and 'Static Phase' are instead just turning yellow and not being filled with any information. This function works on other designs, but does not on this one. Does anybody have any suggestions why this might be happening?
Thanks.
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In orcad17.2 capture, how can one of the overlapping objects (components, or characters) be selected?
In orcad17.2 capture, how can one of the overlapping objects (components, or characters) be selected?
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Etch Length vs Rdly actual length
To preface, I'm not a layout engineer, and I have little experience with layout tools. That said, I'm using the Allegro free viewer to look at a BRD file for a Xilinx eval board. I get how relative prop delay constraints work, but I'm confused as to the results I see in the report file. Can someone explain the difference between the "Total etch length" and the "actual" length shown in the (RDly) line?
Thanks.
Item 57 < NET >
Net Name: FMC_HPC0_LA10_N
Member of Diff Pair: FMC_HPC0_LA10
Member of Bus: FMC_HPC0_LA_BUS
Pin count: 2
Via count: 2
Total etch length: 9052.231129
Total manhattan length: 4784.469 MIL
Percent manhattan: 189.20%
Pin Type SigNoise Model Location
--- ---- -------------- --------
U1.W4 BI (2899.0450 -4363.4860)
J5.C15 BI (3685.0000 -8362.0000)
No connections remaining
Properties attached to net
ECL
NO_TEST
BUS_NAME = FMC_HPC0_LA_BUS
TS_ALLOWED = ANYWHERE
RATSNEST_SCHEDULE = MIN_TREE
DIFFP_PHASE_TOL = 5 mil
Electrical Constraints assigned to net FMC_HPC0_LA10_N
relative prop delay: global group MG_FMC_HPC0_LA_BUS from J5.C15 to U1.W4 delta=0.0000 MIL tol=50.0000 MIL
static diff pair phase tolerance: 5 mil
pin order type: minimum tree
Constraint information:
(RDly) J5.C15 to U1.W4 min= 9615.1448 MIL max= 9715.1448 MIL actual= 9616.0783 MIL
target= (FMC_HPC0_LA29_P) J5.G30 to U1.U9
(3685.0000,-8362.0000) pin J5.C15,BI,TOP/TOP
35.3553 MIL cline TOP
(3710.0000,-8337.0000) via TOP/BOTTOM
8989.42 MIL cline 05_SIG2
(2918.4592,-4382.9002) via TOP/BOTTOM
27.4558 MIL cline TOP
(2899.0450,-4363.4860) pin U1.W4,BI,TOP/TOP,pin+Zall=563.8472 MIL
(SPhase) J5.C15 to U1.W4 min= 9612.0697 MIL max= 9622.0697 MIL actual= 9616.0783 MIL
DPData: gap=var (--0.0001,+0.0000) tolerance= 5.0000; max uncoupled= -0.0001
(3685.0000,-8362.0000) pin J5.C15,BI,TOP/TOP
35.3553 MIL cline TOP
(3710.0000,-8337.0000) via TOP/BOTTOM
8989.42 MIL cline 05_SIG2
(2918.4592,-4382.9002) via TOP/BOTTOM
27.4558 MIL cline TOP
(2899.0450,-4363.4860) pin U1.W4,BI,TOP/TOP,pin+Zall=563.8472 MIL
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Can you create a non-standard shaped plated slot?
All,
I am looking to create some conductive/plated slots that are shaped as three sides of a rectangle. I understand how to do a single one directional slot, but would like advice on how to go about creating a complex shaped slot.
Bonus question:
Is there a standard manufacturing process of either placing a solid copper slug within a plated slot or completely filling a plated slot with solder?
Thanks ahead of time for your time and responses.
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CIP error when searching in Distributor Search
Hi,
when I try to search in Distributor for some distributors I encounter errors. For digikey the error is "Invalid Partner Information", for Newark "The request was aborted: could not create SSL/TLS secure channel." and Arrow simply does not respond. The CIP version is 4.3. Does anybody some idea?
Below the picture about errors
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How to remove thru-hole pads from pastemask layer
I have translated a PADS design into OrCAD PCB Designer 17.2. I now have everything the way I want it, saved as a .brd file, except that thru-hole pads appear on the top pastemask layer. For unknown reason they do not show up on the bottom pastemask layer, which is good. I want solder paste for my SMD pins, but I don't want paste getting into the holes of my thru-hole pads. I did not assign any additional layers at the padstack or symbol level (on Pad Editor, Mask Layers tab, all layers show "None" under the Pad column). I've been digging around and searching the forum, but cannot see how I can safely remove the thru-hole pads from the pastemask layers. The pastemask over the thru-hole pads is the same as the pad diameter. They show on my new Gerber files, but the original Gerbers from the PADS design only has SMD pads on the pastemask layer. Any guidance would be appreciated.
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Placement Edit Persistent Snap
Up until recently I've been able to select a symbol for placement edit and OrCAD would automatically snap to the symbol origin for the point to move. Now, however, lately I've noticed that when I perform the same task wherever I click within the symbol is where the symbol is moved from. It no longer snaps to the symbol origin, which for me is the symbol center. I've tried using Persistent Snap and click on Snap to Symbol Origin, but I get the following error in the command window Could not satisfy the snap condition using 'Symbol Origin' mode.
Could someone help me discern why this has changed and is there a way to change it back so that I can move a symbol based on the symbol's origin? Thank you.
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OrCAD License issue
I am using OrCAD PCB 17.2 dongle based license. I was pointing to the server for the license. Since we got a new pspice license in another dongle, I wanted to use it via another server PC. Now I have changed both user and system variable by pointing to the server, but, my PC is still fetching the old license. I made sure I am pointing only to the new pspice license. Surprising is that when I login with admin it will access the new license, but when accessed through user it will access the old license.
I there any place where the tool will store the licensing information like a cache or anything? Because I don't know how it is still pointing to my old server when I have removed all the settings. After pointing to the new server I even restarted my PC.
To try the last resort, I installed the dongle in my PC and configured the license. This is working fine in only admin and the user login still points to the old server(both user and system variables are pointing only to my PC name).
Kindly help me on this.
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Select a specific property in a component group
Hello,
I am using Allegro Design Entry HDL 17.2-2016.
Let's say I want to select all the VALUE properties of all resistors using the console window.
Is there any way of using FIND, select all resistors and then add all the VALUE properties attached to all the components of the group?
I know it must be possible, but I cannot figure out how.
Thanks in advance,
Daniel
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Some Vias in Net Showing Cross And Others Not
Hello,
I am using Allegro 16.6 and have finished a PCB but after checking it over I am a little confused as to why some vias on the GND net show a cross over them (I guess this indicates they're connected to the GND plane?) but others do not. The crosses seem to be affected by the views drop down menu in the visibilty window. I also see that the power planes on power layers don't show any clearance around vias that aren't on the net of the plane, but all other shapes have some clearance around the vias. Is this normal? I don't have any indication that there are unconnected nets or shorts, but I cannot figure this out. What exactly does it mean if there is a cross? Is it possible for the via to be connected if it doesn't show the cross? I want to be sure everything is in order before exporting gerbers to the board house. Thanks
-John
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Loads of ratsnests after changing component/footprint.
New week, new problem. The community here on these forums has been amazing at helping me with any issues I've run into so far. I've completed the changes on one board already! Now, i'm onto the second board, and I'm just adding one of the same components as last time, but to a different board. I went about it the exact same way as last time, only this time it's created loads of ratsnest in places that are not near the new connector. I don't think this happened on the last board, and takes what should be a one afternoon job, and is going to turn it into a few weeks (for someone like me). Did I do something wrong this time? Or did I just get lucky last time.
What I did:
-updated footprint of old connector in ORCAD Capture by creating the footprint in pcb designer.(same number of pins)
-create netlist from newly saved .dsn file.
-open new .brd that was generated in PCB Designer.
This created LOADS of ratsnest. I then opened the original .brd file in pcb designer and selected everything in general edit mode and selected "unfix". I remade the netslist now, and there are still all sorts of new ratsnests, but not as many as the previous export.
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OrCAD transfer occ. prop. to instance
hi sir
when I do the transfer occ. prop. to instance operation, I found that only "Part reference" and "PCB footprint" will be replaced by occ. property. So, how can I transfer all occ. property to instance, including customer's property?
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Perception EDAC problem and need hotfix verion 40 for 17.2
Hi,
I have problem with EDAC connector when I use Cadence 17.2 (052) hotfix.
It works with bare basic installation of 17.2 (000) and one person in the company have hotfix 40 and it seems to work too.
Anybody is use EDAC connector? Please give me some ideas.
And how can I down load an older version of hotfix?
Thanks,
Regards,
TiBo
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Spectra Auto Router
In the past I have used MakeDo to generate and edit my .do files. Unfortunately, it has been a couple of years since I needed it and my company let the license expire without notifying us. EMA Design Automation has discontinued its relationship with Dave Price and his web site contains non-working phone numbers. I did some searching on the net but could not find any more information on him or his product.
Does anyone know if Dave is still in business? If not is there a similar software package anyone here is using that works?
Thanks
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Change component references and back annotation
Hello.
I've a PCB (Orcad PCB) with connectors named: J1, J2, U3 (!), U4....schematic also have it.
I want to change ref. designator into CN1, CN2, CN3
If I do it from schematic side I found component unplaced.
Some idea?
Thanks
Stefano
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