Hello,
I've a pcb board with routing completed in Orcad PCB 17.2
Rules are: trace with 8mils, trace clearances 8mils.
I routed the board in mils and all sounds good.
Now, I've to do some change in mechanical quote (board and hole places)...but...if I switch to mm and back to mils....there are a lot of inaccuracies error...like "Clearences are 7.999mils and not 8mils"
How to solve? In Mentor PADS and in Altium Designer there aren't these problems.
Thank you
Stefano
Does orCAD support linux ?
Yes, I've made sure that the included paths in Capture.ini are correct. Yes I selected the correct ini (used to one printed out in the session log field at Capture startup). Yes, I've even tested a footprint known to work in PCB Editor (EMC0402) but it fails to show up in Capture when I click "Show Footprint"
I get the following message in the Show Footprint screen:
"Could not launch footprint, see Capture session log for more details."
Then when I look in the session log, it says:
"Parrent Schematic Occurence is NULL"
Yes, those spelling errors are not my typos, its a direct copy-paste from the log. I tried to google that specific error message and I get zero results. I have no idea what the issue is. Any ideas? Because I'm at a loss.
Thanks,
Hello,
I've a multilayer board (Orcad PCB Professional 17.2).
I checked the boxes in Cross Section Editor for Unused Pad (& Via) Suppression...I checked Dynamic unused pad suppression box (global flag)...but...on my pcb I see all pads in any inner layer.
Where's the mistake? Some "user parameter" to check?
Thank you
Stefano
I have been reviewing my company's footprints and found there are several different styles for the thermal pad, especially when vias are added. I'd like to see if there's a consensus on the best way to make footprints with thermal pads. Thanks in advance for any time to help me figure out if there is one superior way to do this.
There has been some related discussion here, but what I found was quite a few years old so Allegro may have changed since then. And I didn't find any suggestions in COS.
Here are the things I've noticed in our company library so far:
-Thermal pad copper element: Some thermal pads are actual pads, others are shapes.
-Via connectivity: Some vias are connected by a cline, others are just sitting in the pad or shape.
-"Via" type in thermal pad: Sometimes there is a single pin (for the symbol pin) and optionally multiple other vias for heatsinking, other times there are only vias.
-Symbol pin connection: The PACK_SHORT property is sometimes used to make a single symbol pin connect to multiple pins under the component. Other times there's a single symbol pin going to just a single element with connectivity in the footprint, with all other elements (vias and shapes and whatnot) deriving connectivity from that single element.
I'm sure there are other differences between our footprints with thermal pads that I haven't seen yet.
In several cases, I see DRC errors in the footprint. These may go away when the footprint is placed on a board, especially if the footprint is placed on a copper shape. However, if the footprint is placed in some empty area of the board and then moved on a shape there may be DRC errors. There can also be issues if the nets of the thermal pad and/or shape the footprint is placed change. I've haven't been able to fully figure this out but it's clear some footprints do better than others at picking up connectivity and not creating DRC errors in the board.
So... I ask you all. What works best? Is there a style that is understood to be superior? Maybe multiple approaches that are equally great?
I want to delete all CLINE Segments of a specific length, e.g. 0.001um. I'm able to select these by query but I can't act on the selection. It seems I'm just able to save or export. I want to select and delete all these CLINE segments. Can someone explain how do do this?
Thanks,
-Bruce
Just reposting this link since there is so much useful info in here. Also search for older presentations as this version has deleted some goodies.
I did STEP Package Mapping as needed. And I view all right on top layer. But if my component is mirrored to bottom layer, then its STEP model not shown. What is my mistake?
I have OrCAD PCB professional 17.2 with hotfix 052.
I have imported the board file which was designed in altium tool. After the successful translation of altium file I found the design extents are very large roughly in -4000000.00 in X,Y coordinate.
If i try to contract the extents i m getting the error as attached in the image.
Is there any possiblity to contract extents ? this issue i m facing when i import altium file to OrCAD PCB
I have OrCAD PCB professional 17.2 H052.
I am facing issue in changing the constraints units in constraint manager of OrCAD Capture 17.2
In the beginning i set the units to be in inches and continued with the design. Later wanted to change the units to mils but i dont find any option to change.
Do help me with this issue.
Hi guys, this is my first post on this forum (YAY)
I am trying to simulate a class D amplifier and I am using IR2110 Chip. This part was not available in the library but I got the .olb and .opj file of this part from digikey. I was somehow able to import the part to use in my schematic and when I tried to simulate it, It says the part/device cannot be simulated. No Pspice template found. I found a few things online that said I have to attach it to a similar part in the library but I cant even find a similar library. What do I need to do? This IC is an integral part of the design so I have to simulate it.
Any Help is greatly appreciated
Thank YouIR2110 - This is the part I need to simulate. This is straight from digikey
Hi all,
Can someone share the specifications of a mid range PC for running Sigrity?
Any Help is greatly appreciated
Thanks,
Eldho
Hi All,
is there a way to add a "matrix" of pins, as needed for BGA packages,
where the Pins are named in a chessboard, like the following?
A0, A1, A2, A3, A4, ...
B0, B1, B2, B3, B4, ...
C0, C1, C2, C3, C4, ...
...
Also: Is there a way to increment in a hexadecimal way, like A0, A1, A2, ..., A8, A9, AA, AB, AC ?
Thank you very much!
Best regards
Janis Weidenauer
Hi,
I am new to OrCAD software and PCB design in general. I have a simple board I would like to design with multiple etch layers (i.e. top, layer2, bottom, all routing layers).
When I use the board wizard I can see all layers on the visibility tab (top, layer2, bottom) and am even able to use vias to route traces between all layers. However, when I use capture to
generate a netlist and open it with my board, the inner layers disappear from the visibility tab. When using auto-routing only the top and bottom layers are used.
Would anyone be able to advise on why I am unable to see/use all the layers I originally made with my board?
Thank you in advance for any assistance.
i have got sch/brd files of xilinx VCU118 dev kit.
since i do not know how to cross probe from DxD to allegro, i have translated DxD (viewdraw) schematic to dsn.
the brd file can be open by allegro 16.6 without any drc problem. but if i import logic from the tanslated orcad generated netlist,
thousands of drc errors would occur. the translation is problematic, to say the least.
so i want to backannotate from this brd file to the translated orcad dsn. normally, backannotate means you have synchronized
from orcad to allegro before, but i didn't ever.
hope i have made myself clear.
Hi team,
We tried to open the BRD file generated by Allegro PCB Designer version 17.2-2016 S048, but failed. Got the error message as
The viewer is just downloaded from website. The version number is 17.2-2016 S015.
Also tried to open this file with Allegro PCB Designer 17.2-2016 P028 [3/31/2016], and still failed.
Would you please advise how to resolve this issue? Thank you.
Best regards,
Beta Chen
Hi! We have the design of a 4-layer fan-out board for a flip-chip design done in Allegro PCB (.brd), but the manufacturer is asking for .mcm files. Is it it possible to convert between them? If so, how? Or does the board would need to be completely designed from scratch in Allegro Package Designer?
Thanks and regards, Jorge.
Hi
I am having difficulty getting a DRC to occur when I stack a microvia on top of a thru via. If the mvia is not stacked then the DRC is getting flagged if it's on the edge of the thru via.
However, when the mvia is coincident with the thru via the DRC goes away.
I *think* I have the DRC setup correct for Same Net checking but am puzzled as to why the overlap is allowed.
Any hints on how to flag overlap of thru to mvia?
Thanks
Hi
Does Allegro Productivity tool box work with Allegro PCB Designer 17.2 Professional license?
Any other configuration need for Allegro Productivity toolbox?
tbx commands are not working. Command not found: tbx panelize
Thanks,
Pradeep
when i use symphony team design to design PCB, client find 0 sever,who can tell me