Hi! Is it possible to export a PCB Designer (.brd) to Package Designer format (.mcm)? (or, equivalently, to import a .brd in Package Designer?)
We have a a 4-layer fan-out board for a flip-chip done in Allegro PCB (.brd), but the manufacturer is asking for .mcm files. Is it it possible to convert between them? Or does the board needs to be completely designed from scratch in Package Designer?
Thanks and regards, Jorge.
Hi Team,
I am trying to create the company logo by importing the .bmp file via File-->import-->Logo. (Mechanical Symbol: Board Geometry-->Silk Screen Top)
But in this method of import the logo creation is not proper.
Does anyone knows any other method for creating proper logo?
Please share me the proper procedure.
I am here with attaching the .bmp file.
Thanks
Amrutha CV
Hello. Starting from hotfix 050 (rare crashes) to hotfix 052 (often) capture crashes while loading projects with pspice templates. If i delete these templates from HDD everything is ok. And when i close the project before exiting then loading of the same project seems to be ok. Our admin tried reinstalling the software but no success. What could solve the issue? Your help is highly appreciated
Dear All,
Our team has develop the PCB design in Version 16.6. I have install the cadence 17.2. When i want to open the Project files(.cpm files) in this version in the Project manager, i got Error, Can't reach this page.
Please provide this remedy.
I am unable import Altium ASCII schematics without an error.
I run "trl altium2hdl advanced" from the command line and select "Allegro Performance" license.
The "Load Altium" step works, it's the "Project Setup" fails.
When I run it from the pull down menus: fle->import->CAD translators->Altium... I get this error: "E-Check if License for FET exist! Check if Template Project exist!"
This is the log file:
X.1.01 INFO - Project Directory set: "M:/A2A/Allegro"
7.3.02 INFO - Altium PrjPCB Definition File Opened!
7.3.02 INFO - Altium PrjStructure Definition File Opened!
7.2.06 INFO - PRJRawList: CDS_Proj_Name: "ian_is_sensor_21041" Proj_Name: "IAN_IS_Sensor_21041" Design_Name: "ian_is_analog_21041"
-------------------------------------------------------------------------------
1.1.0 INFO - [ 1] of [ 2] Start to Load "ian_is_analog_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_Analog_21041.SchDoc"
-->1.4.01 INFO - 48 Parts in the Altium Schematic "ian_is_analog_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
1.1.0 INFO - [ 2] of [ 7] Start to Load "IAN_IS_Ultrasonic_TM_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_Ultrasonic_TM_21041.SchDoc"
-->1.4.01 INFO - 69 Parts in the Altium Schematic "IAN_IS_Ultrasonic_TM_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
1.1.0 INFO - [ 3] of [ 7] Start to Load "IAN_IS_Sensors_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_Sensors_21041.SchDoc"
-->1.4.01 INFO - 26 Parts in the Altium Schematic "IAN_IS_Sensors_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
1.1.0 INFO - [ 4] of [ 7] Start to Load "IAN_IS_Wake_Serial_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_Wake_Serial_21041.SchDoc"
-->1.4.01 INFO - 40 Parts in the Altium Schematic "IAN_IS_Wake_Serial_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
1.1.0 INFO - [ 5] of [ 7] Start to Load "IAN_IS_Power_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_Power_21041.SchDoc"
-->1.4.01 INFO - 57 Parts in the Altium Schematic "IAN_IS_Power_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
1.1.0 INFO - [ 6] of [ 7] Start to Load "IAN_IS_BLE_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_BLE_21041.SchDoc"
-->1.4.01 INFO - 9 Parts in the Altium Schematic "IAN_IS_BLE_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
1.1.0 INFO - [ 7] of [ 7] Start to Load "IAN_IS_CPU_21041" SCH File "M:/A2A/Altium/IAN_IS_Sensor_21041/IAN_IS_CPU_21041.SchDoc"
-->1.4.01 INFO - 25 Parts in the Altium Schematic "IAN_IS_CPU_21041"!
-----------------------------------------------------------
-------------------------------------------------------------------------------
-->3.1.11 ERROR - Project Structure for Design: "ian_is_analog_21041" NOT CREATED
csnetlister.log
csnetlister 16.6-S074 (v16-6-112GH) 7/11/2016
Error loading page.map file for block 'top'. You may wither correct the file or delete the map file. If you choose to delete map file, you will need to purge the page mapping using 'page forcereset all' command.Netlist Log File: temp/csnetlister.log
csnetlister.exe exited with errors.
Thanks,
Richard
which property can be used to avoid package keepouT top to Placebound Top DRC
Greetings -
I have several ".color" files I use to quickly change views in Allegro. When I go to the "view" pull down in the visibility tab I can select them and toggle class/sub-classes on and off quickly. (see below for contents of and example .color file.)
Something changed recently and now when I pick one of these views from the pull down, the relevant sub-classes display on the screen for about 1/2 a second and then disappear. Picking the view a second time results the sub-classes displaying properly. In other words, in order for the display to work correctly, I have to pick the view twice in a row.
I have a feeling a recent change to a user parameter upset this behavior but I can't seem to find which on it is as this was all working fine until a week or two ago. Any ideas would be appreciated. I'm running Allegro 17.2-2016 with Concept/HDL.
my .color files all look something like this:
# View replacement method:
# Partial with toggle
color -toggle "PACKAGE GEOMETRY/ASSEMBLY_TOP"
setwindow pcb
Thanks!
which property can be used to avoid package keepout top to Placebound Top DRC
When generating Gerbers, is there a way to set the "Prefix" cell (or Suffix, for that matter) to the board's filename? This way it will automatically update as revision numbers change, and doesn't have to be manually updated?
For instance set it as $FILENAME_ so if the filename is jim_pcb_v00.brd the gerbers become jim_pcb_v00_top, jim_pcb_v00_bot, etc. but if updated to v01, they will become jim_pcb_v01_top, jim_pcb_v01_bot etc, without having to manually update the Suffix cell highlighted below?
hello.
i want to spread clines with equal spacing. i do know how to spread clines between vias.
but i am just wondering if i could spread clines between the two end clines.
for instance, there are 4 clines but the inner 3 spaces are not equal so i want to move the inner 2 clines to make the 3 spaces equal.
hello
i accidentally deassigned a net on a cline which is connected to a via and a pin.
how can i assign the original net back to the cline whose net was remved?
hello
Is there any way that i can change the radius of the arc on dynamic shapes?
If so, can you tell me how?
We do quite a lot of designs where we use the trace resistance to balance diodes in parallel for DC currents. Is there any way we can set the a impedance constraint for this so we can control the lengths automatically? Since we vary the width on these traces and mix them with copper polygons, we cannot simply set a track length constraint... We'd need to have a constraint on total resistance from end to end on a single net.
Best regards, Mysil
Our virus software is deleting our down loads right after it finishes. We get this message
PUA 'Generic ML PUA' detected on Hotfix_SPB17.20.050_wint_1of1 https://community.sophos.com/kb/en-us/128136
I have sent this to EMA but have yet to receive a reply.
Hi It is my first time using Pspice simulation and I encountered some issues.
Could anyone help me to take a look if there is anything I didn't config correctly in the spice model?
Thx.
** Creating circuit file "Test.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
.LIB "../../../lib/lmh6553.lib"
* From [PSPICE NETLIST] section of C:\SPB_DATA\cdssetup\OrCAD_PSpice\17.2.0\PSpice.ini file:
.lib "nom.lib"
*Analysis directives:
.TRAN 0 100ns 0
.OPTIONS ADVCONV
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source SIMULATION
V_V4 N13378 0 6Vdc
R_R65 N13358 A1_INP 499 TC=0,0
R_R71 N13436 N13378 4.99k TC=0,0
R_R68 A_OUTN N13358 536 TC=0,0
R_R63 0 A1_INP 56.2 TC=0,0
V_V5 N13858 0 1.9Vdc
V_V2 A1_INP 0 DC 1.9Vdc AC 0.25Vac
R_R66 N13962 A1_INN 499 TC=0,0
C_C278 0 N13762 10.1u TC=0,0
R_R64 A1_INN 0 56.2 TC=0,0
C_C281 ADC1_AIN_N ADC1_AIN_P 5p TC=0,0
C_C275 0 A1_INP 1p TC=0,0
V_V6 A1_INN 0 DC 1.9Vdc AC 0.25Vac
R_R67 A_OUTP N13962 536 TC=0,0
R_R72 0 N13436 4.42k TC=0,0
R_R69 ADC1_AIN_P A_OUTP 49.9 TC=0,0
C_C280 N13378 N13762 0.1u TC=0,0
C_C277 N13858 0 0.01u TC=0,0
C_C279 0 N13378 10.1u TC=0,0
R_R70 ADC1_AIN_N A_OUTN 49.9 TC=0,0
V_V3 N13762 0 -6Vdc
C_C276 A1_INN 0 1p TC=0,0
X_U1 N13378 N13762 N13358 N13962 A_OUTN A_OUTP N13858 N13436 LMH6553
**** RESUMING Test.cir ****
.END
X_U1.q9 X_U1.a140 N13858 X_U1.a149 0 X_U1.NPNXTR
X_U1.q1 X_U1.a176 X_U1.a134 X_U1.a252 0 X_U1.NPNXTR
X_U1.q10 X_U1.a146 X_U1.a148 X_U1.a174 0 X_U1.NPNXTR
X_U1.q11 X_U1.a149 X_U1.a134 X_U1.a222 0 X_U1.NPNXTR
X_U1.q3 X_U1.a119 X_U1.a111 X_U1.a154 0 X_U1.PNPXTR
X_U1.q5 X_U1.a111 X_U1.a111 X_U1.a157 0 X_U1.PNPXTR
X_U1.q4 X_U1.a199 X_U1.a111 X_U1.a160 0 X_U1.PNPXTR
X_U1.v2 X_U1.a241 X_U1.a174 0
X_U1.v1 X_U1.a202 X_U1.a176 0
X_U1.i9 X_U1.a0100 X_U1.a0198 2.5e-6
X_U1.i5 N13378 X_U1.a148 12e-6
X_U1.i0 N13378 X_U1.a108 7e-3
X_U1.f2 0 X_U1.a203 X_U1.v2 1.0
X_U1.f3 0 X_U1.a205 X_U1.v2 1.0
X_U1.f1 0 X_U1.a205 X_U1.v1 -2.0
X_U1.f0 0 X_U1.a203 X_U1.v1 2.0
X_U1.rtm 0 X_U1.a205 128e3
X_U1.r29 X_U1.a222 N13762 250
X_U1.r30 X_U1.a224 N13762 250
X_U1.r31 N13378 X_U1.a113 250
X_U1.rtp X_U1.a203 0 128e3
X_U1.r32 N13378 X_U1.a115 250
X_U1.r20 N13378 X_U1.a157 250
X_U1.r15 X_U1.a0113 X_U1.a148 2.5e3
X_U1.r22 N13378 X_U1.a160 175
X_U1.r16 X_U1.a148 X_U1.a0117 2.5e3
X_U1.r33 X_U1.a149 X_U1.a241 200
X_U1.rtc X_U1.a108 N13762 14.3 tc1
-------------------------------$
ERROR(ORPSIM-16015): Unknown parameter.
In allegro17.2 HF052,After opening the automatic teardrop, moving the via around the teardrop will run around
Hi All, Does anyone have a method to highlight all Untested nets simultaneously? I’ve generated automatic testpoints. Now I simply want to see a board view (zoom fit) of the remaining untested nets. I can’t seem to put a Find by Query together that satisfies my requisite. Fyi: I’m aware of the manual (Scan and highlight) function. Thanks for your help/suggestions.
Hello,
I was wondering if it is possible to move the specified path for PCB Footprint symbol. I have selected the default during the installation. Was wondering if its possible to specify to a different path for example a mapped network drive.
Thank You
hello
i started to working on a design file which was worked by a different person.
whenever i try to save a file, it says, "performing a partial design check before saving."
where can i find a setup for not performing a design check before saving?
community.cadence.com/.../pcbboard.zip
hi guys, I am new to Cadence and PCB manufacturing, I designed a digital clock and did a 4 layer pcb for it. When I run DRC it shows some kind of error with shapes in my thru pins. I don't know how to fix this, I have attached the board with this post. I have 4 layers but components are only in top layer. middle layers are VCC and GND. I gave this to a few manufacturing companies to check and they said it had no issues but allegro PCB is still showing errors. can you guys take a look?
EDIT: This is the error I get it: error message It has some design constraint error. how to fix?
Any help is greatly appreciated