Folks,
I know one can create an Excel-like spreadsheet bill of materials (BOM) importing the tab or CSV delimited ASCII BOM file from Allegro Capture (OrCAD Capture) to a get your standard BOM document, but what if you use LibreOffice or OpenOffice type office applications, is there a way to get Allegro or OrCAD Capture to automatically open in LibreOffice Calc when one checks "open in Excel" check mark to create the BOM? Assume SPB 17.20.060 and the latest LibreOffice (version 6.3.2).
CT
Hello,
Pls help to understand the high-level differences of 16.6 vs 17.2 release.
I am trying to open .edn and .eds in OrCAD but I am having no success at either. Is there a converter that I am missing? Is OrCAD able to open these types of files?
I have a number of differential pairs in my design, which are created in Capture from Tools->Create Differential Pair. I was going to create another pair and noticed that the menu item is suddenly grayed out.
When looking into the Constraint Manager I could also see that the pairs I had created earlier were "broken". All I know is that I was flipping a CM choke in the pair and adding some new net names.
DP1+ and DP1- were originally a diff pair. I then flipped the choke (1 <-> 4 and 2<->3) and added the DP1_CM+ and DP1_CM- net names. Well, something like that. Anyhow, in the Constraint Manager I can see that DP1+ and DP1_CM+ are now suddenly defined as a pair. What is going on here??
Hi
I have a 4 layer (Top, Layer1, Layer2, Bottom) rigid board and the internal 2 layers(Layer1, Layer2) from this rigid pcb continue as flex PCB. I have to order a stencil for this board.
I can generate gerber files for solder paste top and bottom but i cannot find any pastemask_layer1 and pastemask_layer2 as there are some pads i need to apply solder paste on. So i was wondering which options i have to check here for generating the solder paste files for these layers.
I am trying to bring in a module to my design but none of the seed circuit components match the design components; even though they are the same p/n.
The reason this is happening I believe is the Device Type names are different. i.e.
The module properties show this for this resistor - Device Type: RES-XX-XXX-XXLF,0,0%,1/10W,11_B
The design that I am trying to bring the module into shows this - Device Type: RES-XX-XXX-XXLF,0,0%,1/10W,11_0603,ACTIVE-11_0603
(I exed out the actual p/n in these examples).
Why is everything after 1/10W different? What controls this setting?
I have Long Name Size set a 255 characters in both designs but the module may have originally been created with something less.
Hello!
I tried to convert Altium Designer schematic into Cadence Capture CIS. I followed the help document step by step, but it failed when I clicked the Translate button like the picture below. The file was converted to ASCII file. Is that a version problem or something wrong with the installation and license?
Hi,
Anyone tell me Allegro PDN Analysis version 16.6 tutorial for performing PI AND PDN Analysis.
Regards,
Srinivas.
Hello Team,
Whenever I launch ORCAD, I see unwanted tools being enabled like pSpice, Alignment, etc. which is not required for my current task. I tried to disable this using customize option but on re-launch, the earlier disabled tools are appearing back.
How can I disable this permanently (at-least till my current task is completed)?
I’m trying to disable this to get wider screen for my design aspects.
With Regards,
Shiva.
This is quite simple, but I can find nothing that tells me what to do...
I have a small board with a filled polygon on the top layer. And traces on the bottom layer. Using through hole components.
The polygon has the correct gap around the through hole pads, vias, etc. UNTIL I MOVE A TRACE. JUST ONE.
Now the polygon has completely filled in.
Is the only way to restore the spacing around the part foot prints, is to DELETE the entire polygon and re-draw it??
In Eagle, it was as simple as clicking the "ratsnest" button and it would re-draw the polygon plane correctly.
What's worse is that now EVERY component pad is shorted out by the polygon plane, and yet the DRC reports no problems.
HUH???
Can someone please explain this, or point me to a useful tutorial?
Thanks.
How do you remove non functional pads from inner layers inside the layout?
Is there anyone out there in mid Michigan and well versed in Cadence Allegro PCB setup and editor that would be available this weekend to make a few bucks teaching an old Altium Designer PCB designer how to use Allegro? please contact me at tashirley@charter.net
My EE's have defined a lot of logical DC net voltages on our boards. Even though I don't use 'true' power planes, the guides for these nets appear as a square with an 'X' in the center of said square. Some of the many voltage nets will be connected on inner layers using areafills. However, a number of voltage nets will be routed as traces. How can I turn on the guides for those nets WITHOUT removing the assigned voltage on those nets?
In the STEP mapping dialog window, what is the difference between "Device Mode" and "Package Mode"?
I guess I'm not familiar with the basic concepts since the help doesn't help me...
Difference between component and symbol definition?
Is it possible to write equations into the command line like : ix (50+50) 30 Where it would result in "ix 100 30 ?
hello
is there a way to set up the spacing for a specific net on a specific layer on the constraint manager?
for instance, i would like to have 100um spacing to GND shapes on L1 layer for clines with net A and 200um spacing to GND shapes on L2 for clines with net A.
(OrCAD version is 16.6)
Hi, there.
I'd like to create a find result report as CSV File, but it can't work.
After choosing 'Save as CSV' is nothing happened on OrCAD.
BTW, creating a find result report as HTML File is OK.
Has anyone solved the same problem before? I'm looking forward to your help.
Hi
I was wondering how can i export a footprint(.dra) file out to .dxf file.
My dxf file comes out to be blank when i run export--> dxf and follow the usual procedure of naming output file and then edit--> select all--> use layer names--> map
and then export
Hi, I am still using Orcad Layout 16.2.0, and I need to use via-in-pad on the next PCB.
I changed the pad attributes of a SMD 0805 resistor, checking the "Allow via under pad" setting in the footprint.
But how I can put the vias under the pads of this footprint in the PCB? I only get errors like "Via will not fit".
Thank you in advance
M.
I have fiducial marks on my board and i am getting error under unassigned shapes/drc as shape to route keepout error. There is no route close to this fiducial.
The orange line is my route keepin boundary. When i move this boundary such that fiducials are outside this boundary, then i am getting
additional errors as shape to route keepin. How to get rid of these?
