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Quoted Identifiers not working with PostgreSQL ODBC

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Attempting to use PostgreSQL with OrCAD CIS. Connection to the database is fine.

The issue occurs when attempt to view data when a table column has uppercase or special characters. Looking at the database logs, it appears that the column names are not wrapped in quotation marks in the SELECT query. Any way to address that? Is this an OrCAD issue or a driver issue?

I have set the "Parse Statements" setting on, but no results.

Environment:

 - PostgreSQL ODBC driver is 12.0.0, 32-bit. I am able to connect to server without issue via driver test. 

 - We're running OrCAD Capture CIS 16.6-S062 (v16.6-112FF). Yeah it's a bit old....

 - Windows 10 Pro, 10.01.18362 Build 18362


Change Delay Tune Colors

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Anyone know if its possible to change the colors on the delay tuning bar that indicate when you're in the correct range? The old one was Red/Orange and the new one in 17.4 Red/Green. I'm a bit color blind and its pretty hard to see the new one. 

Are there any standard PCB Design Rules

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I have designed several PCBs for various projects using Eagle in the past, but I have never really followed any specific design rules.

I was wondering if there are any specific design rules for PCBs regarding placement of components, layers, designing power planes, rules for preventing noise,etc.

I know a few basics such as thicker lines for power rails, place I/O connectors towards the edge. But I want to learn more than just the basics.

I guess the rules may vary depending on the application. For example a PCB with a lot of RF components would follow a few different rules as compared to a PCB used in robotic actuation.

Are there any resources or good books that I could read in order to improve my PCB design skills?

Soldermask Clearance On Planes Causes Increased Pad Size

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We always have in our designs situations where one pin of a row of SMD discretes (mostly 0201's) is tied to a solid plane of copper with no thermals. Over the years, our fab houses flag this and have requested to adjust the mask opening on the plane connection to make it smaller so that it doesn't become a larger 'pad' than the other side of the discrete. We've had this done this successfully over the years. The question has arisen whether we could make this adjustment ourselves within Allegro so that the fab house doesn't have to do it. I can't think of a quick and easy way to do this. How does everyone else accomplish this? Thanks for any insight you can offer.

Decoupling capacitors and ground planes

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I'm making my first ever PCB, a very simple programming board for ATMEGA328p chips. I've got decoupling caps either side of the chip between +5V and GND.

Question I have is that I'm using a copper pour on the top layer as a ground plane, and as well as the ground pin on the capacitors being connected to ground, the actual ground pin on the IC itself is also connected to ground.

Is that an issue? Should the only connection to ground come from the capacitor?

SI ANALYSIS CAPABILITIES IN ALLEGRO PCB EDITOR

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How much frequency support in Si Analysis tool availabel inside Allegro PCB editor ?

3D Viewer on Windows 7 Virtualbox VM - Viewer crashes when using bends

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I'm running Allegro 17.2 inside a Windows 7 VM on a MacOS host. 

The Windows 7 VM has the following specs:

  • 256 MB Video Memory
  • 8 GB RAM
  • 56 GB SSD

I've done testing with and without 3D Video Accelration enabled.

Even with the most basic FlexPCB design, when I start to bend, the program hangs and eventually crashes. For example, below I tried a small bend to start, but then the hourglass hits and I'm stuck waiting until I kill the program:

 Has anyone seen similar behavior? Is there an easy fix to this, or is the bend feature in the 3D viewer too intensive to run inside a VM, and has to be a ran natively?

Thanks,

Jim

Creating a BOM with LibreOffice Calc versus MS Office Excel!!!

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I know one can create an Excel-like spreadsheet bill of materials (BOM) importing the tab or CSV delimited ASCII BOM file from Allegro Capture (OrCAD Capture) to a get your standard BOM document, but what if you use LibreOffice or OpenOffice type office applications, is there a way to get Allegro or OrCAD Capture to automatically open in LibreOffice Calc when one checks "open in Excel" check mark to create the BOM?  Assume SPB 17.20.060 and the latest LibreOffice (version 6.3.2).


SMD pin to SMD pin DRC errors when adding teardrops

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When adding teardrops to SMD pads it seems like they become a part of the pad. This leads to SMD pin to SMD pin spacing DRC errors since the pads have suddenly increased in size. Is there a way to avoid this?

Problem generating PDF files with Nordcad PDF Generation utility

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Hi <

Anyone else having a problem generating PDF files with Nordcad PDF Generation utility ? it works ok on windows 8.1 but not on windows 10. I get the following problem.

Running PDF generation utility 4.05 - (C)Nordcad Systems A/S - info@nordcad.dk

*Error* fprintf/sprintf: format spec. incompatible with data - "Format is '%s/ns_tmp', argument #1 is nil"

Flex PCB Design - How to calculate inner radius when only outer radius is known.

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When adding bends in a flex PCB design, how can we calculate the necessary inner radius if we have a specific outer radius in mind?

Intuitively I would think the outer radius = inner radius + flex pcb thickness, which would be pulled from the stackup. But that doesn't seem to be how it is calculated.

For instance, a simplified model shown below. Here, the flex PCB is 0.25 mm thick. We want to fit a 6.00 mm curve, so we easily calculate the inner radius as 5.75 mm.

tldr: how does Allegro calculate the difference between the inner and outer radius on a bend?

OrCAD Capture 17.4 Dark theme

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I installed the latest OrCAD 17.4 on my Windows 10 PC and the OrCAD Capture GUI is dark theme. I don't like it. Does anyone know how to change it? Thanks.

Bruce 

Drill file error

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Hi

I am trying to generate drill file for my board and the drills are shown quite huge when i see them in View Mate. 

Drill log is as:

Processing NC Parameters file 'nc_param.txt' ...

NC PARAMETERS
-------------

FORMAT 3.5
MACHINE-OFFSET x:0.00000 y:0.00000 (mm)
FEEDRATE 1
COORDINATES ABSOLUTE
OUTPUT-UNITS METRIC
TOOL-ORDER INCREASING
REPEAT-CODES NO
SUPPRESS-LEAD-ZEROES YES
SUPPRESS-TRAIL-ZEROES NO
SUPPRESS-EQUAL NO
TOOL-SELECT YES
HEADER none
LEADER 12
CODE ASCII
SEPARATE NO
SEPARATE-ROUTING NO
OPTIMIZE_DRILLING YES
ENHANCED_EXCELLON YES
SCALE 1.000000

WARNING(SPMHMF-368): Cannot find NC Drill tool file 'nc_tools.txt'
WARNING(SPMHMF-369): ... will auto-generate tool file 'nc_tools_auto.txt'.


Auto-generating tool file 'nc_tools_auto.txt' ...

Size Plating Tool + Tolerance - Tolerance

0.3000 P T01 0.000000 0.000000
0.8001 P T02 0.000000 0.000000
0.9000 P T03 0.000000 0.000000
1.0000 P T04 0.000000 0.000000
1.0201 P T05 0.000000 0.000000
3.1000 P T06 0.050000 0.050000
3.1999 P T07 0.000000 0.000000
1.0201 N T08 0.000000 0.000000
3.1700 N T09 0.000000 0.000000


Drill files being output to directory 'C:/OrcadDrive/OrcadData/DVL/Testboards/AD2CPJigBoard/allegro' ...

'AD2CPJIGBOARD-1-6.drl' created for holes connecting TOP and BOTTOM
-------------------------------------------------------------------

Tool Num Size +/- Tolerance Plating Quantity

T01 1. 0.3000 0.0000/ 0.0000 PLATED 7
T02 2. 0.8001 0.0000/ 0.0000 PLATED 52
T03 3. 0.9000 0.0000/ 0.0000 PLATED 38
T04 4. 1.0000 0.0000/ 0.0000 PLATED 31
T05 5. 1.0201 0.0000/ 0.0000 PLATED 56
T06 6. 3.1000 0.0500/ 0.0500 PLATED 2
T07 7. 3.1999 0.0000/ 0.0000 PLATED 5
T08 8. 1.0201 0.0000/ 0.0000 NON_PLATED 8
T09 9. 3.1700 0.0000/ 0.0000 NON_PLATED 10

---- Total holes: 209

---- Total head travel: 7.40 feet (2.25 meters)

And the NC_param is :

INTEGER-PLACES 3
DECIMAL-PLACES 5
X-OFFSET 0.000000
Y-OFFSET 0.000000
FEEDRATE 1
COORDINATES ABSOLUTE
OUTPUT-UNITS METRIC
TOOL-ORDER INCREASING
REPEAT-CODES NO
SUPPRESS-LEAD-ZEROES YES
SUPPRESS-TRAIL-ZEROES NO
SUPPRESS-EQUAL NO
TOOL-SELECT YES
OPTIMIZE_DRILLING YES
ENHANCED_EXCELLON YES
HEADER none
LEADER 12
CODE ASCII
SEPARATE NO
SEPARATE-ROUTING NO
DRILLING LAYER-PAIR
BACKDRILL NO
CAVITY NO
COUNTER NO
TOLERANCE_DRILL NO
TOLERANCE_TRAVEL NO
TOOL_SIZE NO
ROTATION NO
NON_STANDARD NO
TOTAL_DRILL NO
SEPARATE_SLOT NO
SUPPRESS_TOLERANCE NO
SUPPRESS_TOOLSIZE NO
SUPPRESS_ROTATION NO

The green area is the actual board layer and the red dots are the drill generated.

Causes and Measures for Poor Tinning in PCB Design

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There are 20 processes in the PCB design and manufacturing process. The bad tinning is really a headache. The poor tin on the circuit board may lead to sand holes, line collapse, line dog teeth, open circuit, and line sand hole lines. If the copper is thin, the hole is copper-free; if the copper is thin, the hole is copper-free. If the copper is thin, the hole is copper-free. If the tin is not clean, the number of times of returning tin will affect the quality of the coating. The problem, therefore, the failure to meet the tin often means that it needs to be re-welded or even abandoned, and needs to be re-made. Therefore, in the PCB industry, it is important to understand the reasons for the bad tin.

The occurrence of poor tinning is generally related to the cleanliness of the surface of the PCB. If there is no pollution, there will be no defects in the tin. Secondly, the flux itself is poor, and the temperature is high. Then the common electrical tin defects in printed circuit boards are mainly reflected in the following points:

1. The plate coating has particulate impurities, or the substrate has polished particles left on the surface of the line during the manufacturing process.
2. The board is covered with grease, impurities, etc., or there is silicone oil residue.
3. There is a sheet of electricity on the surface of the board, and there is grain impurities on the surface of the board.
4. The high-potential coating is rough, and there is a phenomenon of burning the plate.
5. The tin surface oxidation of the substrate or part and the darkening of the copper surface are serious.
6. One side of the coating is complete, one side is poorly plated, and the low potential hole has obvious bright edges.
7. The low potential hole has a bright edge phenomenon, the high potential plating is rough, and there is a burning phenomenon.
8. There is no guarantee of sufficient temperature or time during the soldering process, or the flux is not being used properly.
9. Low-potential large-area plating is not tinned, the surface of the board is slightly dark red or red, one side is completely plated, and one side is poorly plated.

The reasons for the poor soldering of the circuit board are mainly reflected in the following points:

1. The bath solution is out of tune, the current density is too small, and the plating time is too short.
2. The anode is too small and unevenly distributed.
3. A small amount or excess of tin light agent.
4. The anode is too long, the current density is too large, the local wire density of the pattern is too thin, and the light agent is out of adjustment.
5. There is a residual film or organic matter locally before plating.
6. The current density is too large and the plating solution is insufficiently filtered.

We have summarized the improvement and prevention of the poor electrical condition of PCB board:

1. Periodic analysis of the composition of the syrup should be added in time to increase the current density and extend the plating time.
2. Check the anode for a reasonable amount of supplemental anode.
3. Hach's groove analysis adjusts the light agent content.
4. Reasonably adjust the distribution of the anode, reduce the current density in an appropriate amount, reasonably design the wiring or panel of the board, and adjust the light agent.
5. Strengthen the pre-plating treatment.
6. Reduce current density, regular maintenance of the filtration system or weak electrolytic treatment.
7. Strictly control the storage time and environmental conditions of the storage process, and the production process is strictly operated.
8. Use solvent to wash debris. If it is silicone oil, then it needs to be cleaned with special cleaning solvent.
9. Control the temperature during the PCB soldering process at 55-80°C and ensure sufficient warm-up time
10. Proper use of flux.

Seven Steps in PCB Design

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PCBs have evolved from single layers to double-sided, multi-layer and flexible, and still maintain their respective trends. Due to the continuous development of high precision, high density and high reliability, the volume is reduced, the cost is reduced, and the performance is improved, so that the printed board still maintains a strong vitality in the development of electronic equipment in the future.

So how is the PCB designed? After reading the following seven steps, you will understand:

1. Preparation in advance

Includes preparation of component libraries and schematics. Before proceeding with PCB design, first prepare the schematic SCH component library and PCB component package library.

The PCB component package library is preferably built by the engineer based on the standard size data of the selected device. In principle, the component package library of the PC is first established, and then the schematic SCH component library is established.

The PCB component package library has higher requirements, which directly affects the PCB installation; the schematic SCH component library requirements are relatively loose, but care should be taken to define the pin attributes and the correspondence with the PCB component package library.

2, PCB structure design

According to the determined board size and various mechanical positioning, draw the PCB frame in the PCB design environment, and place the required connectors, buttons/switches, screw holes, assembly holes, etc. according to the positioning requirements.

Fully consider and determine the wiring area and non-wiring area (such as the extent of the screw hole is a non-wiring area).

3, PCB layout design

The layout design is to place the device in the PCB frame according to the design requirements. Generate a netlist in the schematic tool and import the netlist into the PCB software. After the network table is successfully imported, it will exist in the software background. Through the Placement operation, all devices can be called out, and there is a flying line prompt connection between each pin. At this time, the device can be laid out.

PCB layout design is the first important process in the entire PCB design process. The more complicated the PCB board, the better the layout can affect the ease of implementation of post-wiring.

Layout design relies on the circuit board designer's circuit foundation and design experience, which is a high level requirement for circuit board designers. The primary circuit board designer has a light experience, suitable for small module layout design or PCB layout design tasks with low board difficulty.

4, PCB layout design

PCB layout design is the most labor-intensive process in the overall PCB design, directly affecting the performance of the PCB.

In the PCB design process, wiring generally has three realms:

The first is Butong, which is the most basic entry requirement for PCB design;

Secondly, the electrical performance is satisfied. This is a standard for measuring whether a PCB board is qualified. After the wiring is completed, the wiring is carefully adjusted to achieve the best electrical performance.

Once again, it is neat and beautiful, chaotic and uncluttered wiring, even if the electrical performance is passed, it will bring great inconvenience to the later reforming and testing and maintenance. The wiring requirements are neat and uniform, and there is no rule in the vertical and horizontal.

5, wiring optimization and silk screen placement

"PCB design is not the best, only better", "PCB design is the art of a defect", mainly because PCB design has to meet the design needs of all aspects of hardware, and individual requirements may be conflicting.

For example, a PCB design project needs to be designed into a 6-layer board after evaluation by the board designer. However, due to cost considerations and the requirement that the product hardware must be designed as a 4-layer board, only the signal shielding ground layer can be sacrificed, resulting in adjacent wiring. Signal crosstalk between layers increases and signal quality decreases.

The general design experience is that the time to optimize the wiring is twice the time of the initial wiring. After the PCB layout optimization is completed, post-processing is required. The first thing to deal with is the silk screen mark on the PCB board surface. The bottom screen silk screen characters need to be mirrored during design to avoid confusion with the top screen printing.

6, network DRC inspection and structural inspection

Quality control is an important part of the PCB design process. The general quality control methods include: design self-inspection, design mutual inspection, expert review meeting, special inspection, etc.

The schematic and structural element diagrams are the most basic design requirements. The network DRC inspection and structural inspection are to confirm that the PCB design meets the two input conditions of the schematic netlist and the structural element diagram.

General board designers will have their own accumulated design quality checklists, some of which are derived from the specifications of the company or department, and others from their own experience. Special inspections include Valor inspection and DFM inspection of the design. These two parts focus on the PCB design output back-end processing lithography files.

7, PCB board

Before the PCB is formally processed, the board designer needs to communicate with the PE of the PCB supplier board to answer the manufacturer's confirmation of the PCB board processing.

These include, but are not limited to, PCB board model selection, line layer line width adjustment, impedance control adjustment, PCB laminate thickness adjustment, surface treatment process, aperture tolerance control and delivery standards.

The above is the entire process of PCB design.


Controlling visibility of individual shapes

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Coming from Altium I'm used to the concept of "Shelving Polygons", which in Allegro language would translate to "Hiding Shapes". In Altium you have a polygon manager where each polygon is listed and where you can control the visibility of each polygon as well as some other parameters. Is there anything similar in Allegro?

I really, really want to control the visibility of individual shapes. I know how to set transparency of shapes, hide all shapes or just hide shapes on a particular layer, but haven't found a way to control individual shapes.

/F

Net names on pins disappear when moving a symbol

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Is there a way to keep the net names on pins visible when moving a symbol? Also, if you have set a custom color for a specific net, that color changes back to the default layer color on the symbol you're moving. Can I change that?

Shape to route keepout gap?

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Hello all,

Im having a hard time figuring out why my copper shapes are not butting up to the route keep outs edge.  Its putting a 0.03 mil gap between them. I assume its a preference setting but i cannot for the life of me find it. Any help would be appreciated. 

Thanks!

Chad

Using Orcad SIGNAL_MODEL attribute?.

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Hello,

We want to set up our Allegro Design Entry(Orcad) libraries so that when forward annotating to Allegro SI (Specctraquest), all parts come with an IBIS and Espice model automatically attached. It is a real hassle to have to manually attach them each time you create a .brd file
I have tried using the SIGNAL_MODEL = attribute in Orcad, in conjunction with a Specctraquest .dml library containing suitably named parts, but with no joy

Anybody got any ideas on how to set this up?

thanks

iosman

TH pin does not connect to a shape of the same assigne net

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I have 3 different TH components that share the same net "AC_N". 

2 components pins connects well to the shape on top layer "AC_N", while the third does not connect.

The global dynamic params are set well to all the other pins, except this.

Any thoughts?

Thanks!

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