hello
i have a problem with the constraint region setting.
I set one region as l/s=50/50um and the other as l/s=10/10um as shown below
but when i connect the two clines over the two regions, the l/s=50/50um constraint takes over on region b as shown below.
is there a way to keep the l/s=50/50um constraint on region a and the l/s=10/10um constraint on region b?
i set the physical and the spacing on the constraint manager as shown below.
I have OrCAD Capture 17.4 p001
In the latest release of 17.4, in capture when a schematic symbol is placed it takes a longer time to get placed (nearly 10-15sec).
Is it an issue with the software. Is there any solution.
I have renamed capture.ini, cleared temp files, deleted capture workspace yet the issue is the same.
Hi
I have a QFN footprint which i want to edit it to another footprint with a little bit different pad sizes.
My question is if i edit this available footprint according to my needs and save it as 'Save as' footprint and provide the necessary pad files to it.
Do i need to make a new .psm file for this new footprint or it will generate automatically. If it needs to be done manually, what would be the
best option to do it?
Thanks
Hi, everyone. I've been away from OrCAD for a while - we switched to Altium about 6 years ago at my old company. I'm on a new job, and I'm re-learning OrCAD again. So, I have lots of stuff to relearn, and I have a lot of stupid questions. The first problem that I can't figure out is how to disable pin numbers or names on components that I don't want them to be visible. For example, every resistor symbol I'm placing on the schematic has the pin numbers visible, and it's annoying and cluttering up the schematic. I'm using OrCAD Capture CIS V17.2. I have notes and training manuals from the old 16.XX version, but a lot of the stuff isn't the same anymore. I know, it's a newbie question, but I'm having a hard time finding the answer. Help! :)
This example is a good starting point if you want to traverse all occurances of each instance, important for exporting BOMs.
C:\Cadence\SPB_17.2\tools\capture\tclscripts\capCustomSamples
So, this example organizes parts by instances and occurrences having to do with CIS. But, can I see the page name from this?
I've changed the code to solve a problem (catching value property updates before Part Manager resets them to match CIS)
But, I need to export the Page Name that these parts are located on in the DSN project. Because finding this part on a huge project is painful when I have to do a lot of them.
Apparently, this is not similar to GetRefDes or GetPartValue (CISBase?)
# pPartID function parameter. Used to get lCISInstOcc
# pPartID is iterated outside this routine
set lUINTPartId [CISTclHelper_sGetUINTFromInt $pPartId]
set lCISInstOcc [$pCISDesign GetPartOccForID $lUINTPartId]
set lCISPartInst [$lCISInstOcc GetOwningCISPartInst]
set lCaptureObjIdUINT [CISTclHelper_sGetUINTFromInt [$lCISInstOcc GetCaptureObjectId]]
#$lCISPartInst GetOccStatus $lCaptureObjIdUINT $lPartStatus $lKey
set lRefDes [$lCISInstOcc GetPartRefDes]
set lRefDes [$lRefDes GetRefDes]
set lRefDes [DboTclHelper_sMakeCString $lRefDes]
set lRefDesStr [DboTclHelper_sGetConstCharPtr $lRefDes]
set lPartValueStr [DboTclHelper_sMakeCString]
set lPartValue [$lCISInstOcc GetPartValue]
set lPartValueStr [DboTclHelper_sGetConstCharPtr $lPartValue ]
This part definitely doesn't work.
ERROR : Invalid method.
set lPageIDStr [DboTclHelper_sMakeCString]
set lPageID [$lCISInstOcc GetOwningPageID]
set lPageIDStr [DboTclHelper_sGetConstCharPtr $lPageID ]
Anyone figure out if I can use GetOwningPageID from an instanceOccurance?
Is there any option for cross probing the dx designer schematic to allegro layout
I am using allegro 17.2 the problem I am facing is when I route the differential pair,
"SigNoise Error/Warning" window appears and hangs the entire system searching for some file, and ends up with this:
E- Field solution failed for STL_1S_1R_9187
E- Field solution failed for STL_1S_1R_9188
E- Field solution failed for STL_1S_1R_9189
E- Field solution failed for STL_1S_1R_9190
E- Field solution failed for STL_1S_1R_9191
E- Field solution failed for STL_1S_1R_9192
E- Field solution failed for STL_1S_1R_9193
E- Field solution failed for STL_1S_1R_9194
E- Field solution failed for STL_1S_1R_9195
E- Field solution failed for STL_1S_1R_9196
E- Field solution failed for STL_1S_1R_9197
E- Field solution failed for STL_1S_1R_9198
E- Field solution failed for STL_1S_1R_9199
E- Field solution failed for STL_1S_1R_9200
E- Field solution failed for STL_1S_1R_9201
E- Field solution failed for STL_1S_1R_9202
E- Field solution failed for STL_1S_1R_9203
E- Field solution failed for STL_1S_1R_9204
E- Field solution failed for STL_1S_1R_9205
E- Field solution failed for STL_1S_1R_9206
E- Field solution failed for STL_1S_1R_9207
E- Field solution failed for STL_1S_1R_9208
E- Field solution failed for STL_1S_1R_9209
E- Field solution failed for STL_1S_1R_9210
E- Field solution failed for STL_1S_1R_9211
E- Field solution failed for STL_1S_1R_9212
E- Field solution failed for STL_1S_1R_9213
E- Field solution failed for STL_1S_1R_9214
E- Field solution failed for STL_1S_1R_9215
E- Field solution failed for STL_1S_1R_9216
E- Field solution failed for STL_1S_1R_9217
E- Field solution failed for STL_1S_1R_9218
E- Field solution failed for STL_1S_1R_9219
E- Field solution failed for STL_1S_1R_9220
E- Field solution failed for STL_1S_1R_9221
E- Field solution failed for STL_1S_1R_9222
E- Field solution failed for STL_1S_1R_9223
E- Field solution failed for STL_1S_1R_9224
E- Field solution failed for STL_1S_1R_9225
E- Field solution failed for STL_1S_1R_9226
E- Field solution failed for STL_1S_1R_9227
E- Field solution failed for STL_1S_1R_9228
E- Field solution failed for STL_1S_1R_9229
E- Field solution failed for STL_1S_1R_9230
E- Field solution failed for STL_1S_1R_9231
E- Field solution failed for STL_1S_1R_9232
E- Field solution failed for STL_1S_1R_9233
E- Field solution failed for STL_1S_1R_9234
E- Field solution failed for STL_1S_1R_9235
E- Field solution failed for STL_1S_1R_9236
E- Field solution failed for STL_1S_1R_9237
E- Field solution failed for STL_1S_1R_9238
E- Field solution failed for STL_1S_1R_9239
E- Field solution failed for STL_1S_1R_9240
E- Field solution failed for STL_1S_1R_9241
E- Field solution failed for STL_1S_1R_9242
E- Field solution failed for STL_1S_1R_9243
E- Field solution failed for STL_1S_1R_9244
E- Field solution failed for STL_1S_1R_9245
Command > `EscEsc
Allegro 17.2 hotfix 062 is giving me multiple problems including file manager, diff pairs, edit properties, right mouse button, etc.
I want to roll back to hotfix 050. What is the safest way to roll back to 050?
Should I reinstall the base and then install hotfix 050?
Thanks
Hi everyone,
I need to import a very specific sized image to my silk layer. It is again due to Altium to OrCAD translation. The image on my Altium board is a 20mm x 6mm box with a string of Arial text in the box. As we know, OrCAD does not support TrueType fonts so I need to create this image in a separate image program like GIMP or Photoshop and then import them into OrCAD. I made the image to the 20mm x 6mm scale in GIMP using 144x144 pixels per mm. This gave a nice resolution to the font. In PCB Designer, when I try to use the method of New->Mechanical symbol then File->Import->Logo, I do not get any ability to set units, only Scaling Factor. What is the scale in reference to?
Is there any really good way to make this logo to be the exact size that I need it to be.
Folks,
Just updated my system to a Windows 10 Professional from Windows 7 Professional. Never had any issues with Cadence SPB 17.2 PSPICE setups until Windows 10. Now everytime I enter data into the Simulation Profile like simulation time, configuration libraries, etc., the Cadence schematic disappears/crashes out with the dialog that it has crashed. Did this on two separate machines with the exact same results - both crash when you start to enter data for the PSPICE simulation. Both systems are using Cadence 17.20.061 OrCAD with PSPICE option and both crash exactly the same way. One system runs one Xeon CPU and the other runs 2 Xeon CPUs. Both systems had no issues with Windows 7 Professional (64-bit).
Is anybody else having this issue with Windows 10? Is there some changes to the Windows 10 environment I need to make to get PSPICE to be stable?
Thanks!
Chris
Hello All,
Just tried to open a schematic marked read-only in our file system. Capture instantly closes the file without a message of any kind in the session log.
As far as I can tell, this is new behavior from 17.2. Is there anything I can check for additional information, or to force Capture to open the file? Marking the file as read-write is not an option.
Thanks!
-Pete
I have recently downloaded the 17.4 trial version to learn this software.
After going through the tutorial on developing a schematic and completing the footprint development, annotation and DRC , I attempted to create a netlist.
The tutorial said that there would be a .brd file created after the netlisting was completed, located in the allegro folder with the pst* files.
The tutorial's instruction show an entire section on the netlist window that include creating or updating PCB Editor Board (Netrev)
When I select the netlist tool, the window I see doesn't have anything below the Netlist Creation. I attemted to upload a picture of what my Create Netlist Window looks like, with no options for creating a .brd file.
Is this something new in 17.4? I found netrev on the C:\Cadence\SPB_17.4\tools\bin path, so it is available.
Thanks
How to generate the S2P file format from power SI tool ?
DOES NETS IN NETLIST FILE "pstxnet" WILL DIFFER FROM SCHEMATIC DESIGN NETS?
DO I HAVE TO CHECK NETLIST AND SCHEMATIC MATCHING OR NOT FOR ANY ERRORS?
Does created netlist from a schematic design in orcade capture will differ each other?
Is there an easy, straightforward way to find footprints for generic packages such as 805 or 1206 in the OrCAD Footprint library. The naming of the footprints in the default library is not straight forward!
WARNING (Layout To Allegro PCB Design), Empty mechanical pins were discarded from footprint 'CONN_11PIN_PLUG_J7'
ERROR (Layout To Allegro PCB Design), Error while writing the PCB Editor Database.
ERROR: Subclass name SOLDERMASK_TOP not valid Allegro subcls for class ETCH. Quitting.
ERROR: loading Allegro database
reply me with solution @ electronics6.4555@gmail.com
Thanks in Advance
Hi everyone,
i tried to export the bottom pad pin number from allegro as DXF file. while import i could not find the Bottom pad pin number in auto cad. i could see the TOP pad pin number in auto cad.
but i could not visible bottom pad or bottom symbol pin number in auto cad. is any special setting is there in allegro ??
Hi, I have put together a three page schematic and the symbols are tiny when placed on the schematic sheet. I used basic symbols straight out of the transistor library and logic library. When I zoom out enough to see the whole sheet and title block, the components are so small that I cannot make them out.
I have the sheet sizes all set for size A, but that doesn't make a difference.
The title block appears to be the correct size for the sheet size I am using. I tried closing and then reopemning the project, hoping that would set everything correctly, but nothing changed.
Hi.
I work with ORCAD PCB Designer Professional 16.6. I tried to import gerbers from altium (with .GBL, . GBS, .GML, .GTL, .GTO, .GTP, .GTS) but I couldn't.
So, it is possible to import that altium gerber files to this version of PCB Editor?
If it is possible, how can I do that?
And if it is not possible, it is possible in other version of PCB Editor or do I need some tool independently PCB Editor version?
Is there a way to convert text into shapes? I've got some text in a symbol file that I'd rather not rely on the design file having the proper dimensions assigned to the text in order for it to show up properly. Seems to me, converting the text into shapes should solve that problem, but I can't find any way to do that.
Thanks,
Mark