Hello,
In Allegro 17.2 , how do I to change the padstack name in a .dra symbol?
Frank
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Allegro 17.2 change padstack in .dra symbol
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How to keep the cline segment when they touch the same net via?
Hi all,
I wonder about the routing skill, I want to keep the straight cline segment when they touch with same net via.
if one of cline contact with via, it connected with via automatically. but if I want to move the cline segment without via (I meant the via fixed at same location), the cline already sticked with via,
so it separated each other and move separately,,,
for easy understanding, I added the captured pics.
1. connect with same net via (with Route Slide Mode)
2. the straight cline is separated automatically
3. so if I want to move downward the straight cline, they move separately (like below pic)
But I want to move like below pic with ignore the connection of via
if you have any good idea, please teach me.
Thank you!
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well tested 0201 symbol footprint
Hello,
Could someone recommend a 0201 footprint that is well proven for good from personal experience for reflow assembly?
Frank
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Capture Canvas Image (Allegro 17.4HF007) broken?
Hi
I'm trying to see one you all out there can try to reproduce this issue I am seeing in Allegro. 17.4 HotFix 007,
Open a design, select "capture canvas image" and it should prompt you to save a bitmap image. My bitmap is junk. All white.
Anyone else? Cadence says it is working fine.
Thanks
redwire
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Boatload of issues when trying to ECO an existing PCB design
Folks, I am seeing a boatload of "file access" issues with a PCB design that I took all the way to artwork generation, and I have done VERY MINOR edits in the schematic, updated the netlist, went back into PCB editor, did minor changes to reflect schematic changes, and then I am trying to re-create manufacturing files, this is where I am seeing multiple issues all seemingly claiming that previously-generated files can no longer be overwritten!!!:
1. I have taken multiple designs before to completion of artwork and manufacturing files generation. Never before I had issues with unrouted connections. Now that I have replaced a few symbols by the ECO operation from schematic entry, and re-positioned them, I see "unrouted" connections show up around these newly placed parts. The "unrouted" connections are super short, I have no idea what Allegro PCB Designer wants, I clearly see copper on top of pin, and I have even "reran" some more copper traces on top of old traces. Allegro PCB Designer stupidly claims that I have missing connection here.
2. If Allegro PCB Designer claims that I have 1% of "unrouted" connections, then how possibly can DRC status be GREEN???
But the absolute show-stopper for me is NC drill files regeneration. I HAVE ALREADY generated these files for previous revision of the design, now re-creating then is impossible!
3. Trying to re-create Artwork apertures I get "Failed to open file". Well, the file IS MOST DEFINITELY THERE, AT THE SPECIFIED LOCATION, AND IT CONTAINS DATA PREVIOUSLY GENERATED IN PREVIOUS REVISION OF THIS DESIGN.
4. TRYING TO RE-CREATE DRILL LEGEND, I GET ERROR "*Error* deleteFile: permission denied - "./nc_param.txt"". Again, this file was already generated during previous manufacturing files generation, it DOES exist, it is in a normal location (my project file, in folder called allegro). OrCAD tries to create a file called nc_param.txt.new.
5. Trying to use NC Parameters window, I get error "Cannot save parameters in that file name".
6. Trying to generate NC Drill files, pressing on Drill button I get NOTHING. Why wouldn't at least a meaningful log be generated? The log that is available is for the previous design iteration, when I was able to generate all manufacturing files successfully.
Did a single setting get garbled up? Paths setting of some sort? I am DIRECTLY pointing Allegro PCB Designer to configuration files, and yet it still claims that it cannot write to those files!
Allegro PCB Designer 17.2-2016 S051 [1/28/2019] Windows SPB 64-bit Edition
community.cadence.com/.../art_5F00_aper.txt
3. 
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Hi, could you please tell me how to clear or delete the DRC constrain setting as shown below. Thanks
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Component offset is step file mapped PCB
I am facing an issue in the step file of the PCB. PCB step file got one component which is shifted from the original location supposed to be.
Attached is the image for reference
Pl help on this.
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Via got deleted
Hello
I selected "all on " on find tab and deleted some portion of layout routing , but this action deleted all the Via's through out the board associated with power net (GND ,VCC)
I didn't noticed this and did good progress in the layout , later I saw just "CLINE" is there on fan-out , no via :( .
Is this a bug ? if its deleted due to selection of net in find tab then cline also should delete !. Causing lot of rework at the end .
Tool Version :17.20
Thanks
Girish
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Searchable PDF's - Ref Des
I used to put a check mark on 'non-vectorized text' in plot setup in order to create searchable assembly drawings, but since I loaded new software some months ago, it's not working properly. The notes on the assembly drawing PDF are searchable, but for some reason, the REF DES are not plotting at all. If I don't check that box, everything prints, but it's not searchable.
I am using: Allegro 17.2-2016 S060 [10/1/2019] Windows SPB 64-bit Edition running on Windows 10.
I am selecting 'Microsoft Print to PDF' as the printer. What changed to cause this issue? Thanks for any feedback you can provide.
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Database Compatibility Mode Converter
Hi everyone!
I have a question to ask for your help.
I have a layout PCB board opened in the compatibility mode (17.4) by Allegro PCB tool 17.4
Now, I want to open it with compatibility mode (17.2) by Allegro PCB tool 17.2 version. I tried to change the mode from 17.4 to 17.2 in Allegro 17.4 but when I opened it by Allegro tool 17.2, it failed. [illustrated below]
I look forward to the help from everyone in this forum, thanks so much!
Best Regards,
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Launching PDF from a link in PDF (Orcad PDF Export)
This post is in response to a youtube video posted by Parallel Systems, UK
https://www.youtube.com/watch?v=vXQCP3ppmDo
At 2:38 the presenter clicks on a part, then clicks on one of the properties (datasheet link) and it spawns the datasheet pdf.
Does anyone know how to make this work?
I've tried Adobe Acrobat Pro DC, but Link: Auto-Create Weblinks from URLs... doesn't do it.
Are there other settings?
This looks like something that is very useful! Should be a customer requirement for the next release!
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Drill Layer Pairs in Orcad Documentation Editor
The question is: how to get Documentation Editor to display drill layer pairs separately in a drill chart?
The drill I have now groups all the same diameter drills into one line and calls the Start and End layers both 0, so Layers 0-0.
In PCB Designer (the layer pairs are correct):
Has anyone else run into this and figured out how to correctly display Layer Pairs?
There should actually be 3 lines for 0.152mm drill, Through, L1-L2, Bottom-L2
TIA for any responses!
(would really like to get a forum for just Documentation Editor going, it's totally a diamond in the rough!)
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new full-featured web complex flowcharting editor has the capacity to evolve into a complementary schematic tool
JDElite Diagram Builder www.jdelite.com is a Web flowchart tool for creating complex graph diagrams.
This is a full-featured editor built on JavaScript/HTML5 with node.js access to the file system.
Its on-screen help and outstanding editing capabilities allow to create quickly and easily flowcharts
of any size and complexity. Its unique feature is that it offers unmatched readability to even the most
complex diagrams. This is achieved by the proprietary algorithms for orthogonal edge routing of directed
graph diagrams with highly efficient edge crossings reduction (patent No. US 10,424,096).
This editor has the capacity to evolve into a complementary schematic tool.
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OrCAD Capture 17.40.008 Very Slow and Clunky Startup
Hi,
Got Windows 10 Pro (64-bit) with last update (2004). Noticed that upon starting the Cadence Capture (OrCAD), that the application seems to take quite a bit of time to get to a stable screeen (>30 seconds). I have disabled the Startup Screen (per the following Forum URL):
and it seems to take the same amount of time to get to the stable screen.
Are there any other things one can disable to speed up the launching of the Capture 17.40 application? BTW, I also have the latest fix (008) installed.
Chris
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Padstack error
Hello,
I'm using Cadence Allegro 17.2
DBDoctor shows a message:
ERROR: in PAD STACK padstack name = EPAD_154X114_15HXD12WARNING(SPMHA1-120): Illegal pad size. Error cannot be fixed.
However, I changed the padstack, changed its name and deleted old. In this case this padstack is absent in my project.
But "Padstack Definition Report" shows it. And DBDoctor also. It means the information about this padstack present somewhere.
The question: How can I delete the information about old padstack from the project database?
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Standard via structure - trace width
Hi
I create "standard via structure" for BGA fanout with trace width 0.2mm ( because I need not standard trace angle between pin and via).
But when I use create fanout command with radio button "standard via structure" - trace width NOT changing in according to my constraints, it stays 0.2mm as when I created via structure.
If I use create fanout command with radio button "via" - trace width changing as I set in constraints.
Could you help me ???? Please !!!
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Using Bend Tool Cuts Flex Instead of Bending
Hi gang,
I have recently discovered the ability to add bends to boards which is great as I have a flex design I'm working on with LOTS of folds and it's very helpful to see how it will look after folding. I currently have about 10 bends set up in the design, and all of them work exactly as you would expect them to except for one where instead of bending the flex at the bend line, it actually cuts the flex at the previous bend line (closer to the anchor point) and then bends, effectively forming two pieces. Even weirder: if I adjust the previous bend line's angle, it bends the flex normally....indicating that it knows the rest of the flex is connected when that bend line gets folded, but then cuts the flex when I try to fold the next bend line. Here's pictures to help illustrate the point:
Bending at the previous bend line everything looks fine:
But bending at the next line cuts the end of the flex off at the previous bend line:
For the record, the PCB is anchored on the section where U3 and those passives are located.
I thought the issue might be related to my outline, but I can't find any gaps (maybe they're there, but I don't see them). I have tried deleting the bend lines and recreating them, even moving the one where it cuts the flex slightly just to see if it would cut it in the new place (it does) because the bends tend to be on vertices in the outline and I thought maybe that had something to do with it. I moved the anchor around to different parts of the flex, and still just this ONE bend line gets cut while the other 9 or so work fine. Anyone got any suggestions?
Any help would be greatly appreciated!
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Allegro PCB reports property "pin pair"
Hi i'm jay,
I am struggling to find the one of property to extract the report.
if I extract the "Etch Length by Pin Pair Report" at the quick report, I can see the "pin pair" property like below pics
so I thought I can customize the list of property that I want to have
I found out the each list at the "Repots" window with "New/Edit" command
I found the Net Name and Etch Length properties but I couldn't find the "Pin Pair" property.....
If you know the location of "Pin Pair", please let me know
Thanks
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how many CPU cores can use for Allegro PCB Editor maximally?
If we suppose we have infinite core on CPU, then How many cores Allegro PCB can use for performance?
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about file size when I use the Microvia
Hi All,
when I used the only microvia for 6 layer PCB board design, my result .brd size was much higher than using BBvia
Do you know some reason about this?
thanks !
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