Import Altium Schematic into Orcad Capture

July 28, 2020, 2:37 am

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Hi everybody,

I am trying to convert an altium project (both schematic and PCB) into Orcad 17.4.

I am following the guide https://www.orcad.com/sites/orcad/files/resources/files/OrCAD_Altium_Migration_Guide.pdf suggested by Cadence, i saved everything in ASCII format and i have the compiled Altium project with the .PrjPcbStructure file.

I translated the PCB without issues and it is perfect, however, when i try to translate the schematic in Orcad Capture, it crashes everytime. I also tried to use the Altium Schematic to HDL Translator in Orcad PCB designer but it 

gives me the following error : "E- Check if license for FET exist!" , "NO License for Project Structure found!".

Can somedoby give me a hint? 

Iknow that there are third parties software that can translate the schematic but is not a viable solution for me.

Thanks

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Dynamic phase tolerance

July 28, 2020, 7:45 am

≫ Next: Symbol Import issue in OrCAD capture CIS 17.4

≪ Previous: Import Altium Schematic into Orcad Capture

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This is the first time I've used the dynamic phase tolerance. I don't have the high speed option, but it does seem to be functioning although it doesn't seem consistent. Meaning I get violations on some pairs, but not on others that look very similar.

My tolerance is set to 15mil and max length is 0.

I thought I understood how it works, but perhaps not. 

This image is directly under the driver.

Symbol Import issue in OrCAD capture CIS 17.4

July 29, 2020, 1:01 am

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Hello Everyone ,

I am using OrCAD capture CIS 17.4 Eval to design a controller board . This is my first time working with OrCAD capture CIS and I am facing a symbol import issue .

When I try to import a Symbol from Ultra Librarian the import process goes on smoothly by following the import guide from UltraLibrarian but when I try to use it in my schematic the pins of the symbol all group to the left side . I don't see this grouping when I import the library for the first time and look at the symbol but after placing the symbol on my schematic this grouping of pins on one side is reflected even in the library. I spent countless hours looking online if anyone faced a similar issue but couldn't find a relevant discussion . Hence , my post. 

I have pasted a screenshot of the issue below :

Thank you for your time and I look forward to any suggestions ,

Best,

SP

difference between the 4 layer & 6 layer

July 29, 2020, 4:17 pm

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Does we select the 4 layer PCB instead of 6 layer PCB?....if i did what will happen in future i mean during the PCB design time.

and the layer selection is based on cost? or else any other specified reason behind there?

Mouse recommendation for Allegro use

July 30, 2020, 7:51 pm

≫ Next: Allegro impedance calculation

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Hello everyone,

I apologize if this is not the right forum to use for this post.

I was wondering if anyone can suggest a specific mouse manufacturer/brand that is best for using with Allegro. I use Allegro 70+ hours a week and I am looking for a type of mouse that helps relief the stress off of my wrist and thumb. My hands are large which puts a lot of stress and strain on my hand and fingers when the mouse size is not proportional.

I tried so many mice but no luck. I also searched online for the best PC mice for CAD engineers and that did not lead anywhere.

So any suggestions would be greatly appreciated.

Thanks in advance.

gbej

Allegro impedance calculation

July 31, 2020, 2:56 am

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Hello,

I have an issue with Allegro calculating the impedances. I have followed this tutorial: https://www.youtube.com/watch?v=XKVQPEIeRT0 but I am getting wrong values. Even if I put same values for cross section as he has in 0:40, mine values for trace thickness with same impedances (and vice versa) are approx. 40 times bigger: https://imgur.com/a/5ktfCpb.

I am assuming there is another settings somewhere which influence this but I am not able to find it. Can someone please help me with this problem?

Thank you in advance.

I am using OrCAD PCB Designer Professional 16.6-2015 S060

how to display the information of bbvia

August 1, 2020, 12:55 am

≫ Next: How to fix the via problem ?

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Hi All,

I created the bbvias on 6 layer board

but as I know, there should displayed the layer information like below on the via pad.

despite of bbvia, however, my allegro PCB wasn't displayed like that...

I add my via pic below

thanks !

How to fix the via problem ?

August 1, 2020, 10:30 am

≫ Next: Orcad CIS part group export to BOM

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I am a self learner trying to duplicate  the reference design from scratch.

Following is the reference design board file via pattern (layer-2 GND plane):

Here, drill and pads of the vias are visible and the clearance with the ground plane is also achieved.

Below one is my PCB design. Here two difference I have noted. First, I am not able to differentiate the drill and pads of the via. Undesirable connections of all vias and mechanical pins to the ground layer is second. Any advice to avoid this situation?

Tool: 17.2

Close up views of vias (layer 2 GND)

Regards,

VT

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Orcad CIS part group export to BOM

August 2, 2020, 4:39 am

≫ Next: Correct use of NET_SPACING_TYPE net property to drive high voltage spacing constraints

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Hi, 

I'm using Capture CIS  V17.XX and would like to export the group allocated in part manager to the CIS BOM. I found no way to do so, as the allocation to group dose not seem to be done by property. 

can someone advise? 

Thanks

Nir

Correct use of NET_SPACING_TYPE net property to drive high voltage spacing constraints

August 3, 2020, 11:46 am

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In hierarchical designs, I have found that engineers are able to assign a single net to different NET_SPACING_TYPE classes at different levels of the schematic hierarchy.  Ultimately,  the flat net can only be assigned to one class.  

Should the Schematic Nets tab or Flat Nets tab be used when editing the NET_SPACING_TYPE properties in a hierarchical schematic?

Thanks!

OrCAD professional fanout etch tuning creating opened nets

August 4, 2020, 1:52 pm

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Hi

I have a weird problem - I'm trying to work on timing a matched group with the relative propagation for the net group.  I did a fanout on my connector and every time I edit the etch the net that I edit the fanout gets modified in such a way that the connectivity gets broken at the pin on the connector that's fanned out.  I also can't see the GUI option that shows me the timing that I'm missing but I'm not sure if that's due to this being a broken net or if is an option I disabled before.

This is a design I've reused a few times so there's probably some stale rules that need to get flushed but this used to work (with the delay tuning tool giving me my +/- tolerances for the net to come up to the spec on the target) and it didn't used to disconnect the net whenever I edited the trace.

I'm using OrCAD professional 17.2

Stacked Conductors or 'Invisible' via

August 6, 2020, 7:13 am

≫ Next: Orcad-Allegro-Highlighting anything really slow after upgrade to 17.4 S008

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• Is it possible to have two conductor layers stack on top of each other (without a dielectric in between them) and have allegro pcb detect connection without vias?

OR

• Is there an 'invisible' via that I can add to constraint manager? By invisible I mean it will not be generated as hole in the drill file but will simply be used for connectivity purposes within Allegro PCB itself  

Orcad-Allegro-Highlighting anything really slow after upgrade to 17.4 S008

August 6, 2020, 8:08 pm

≫ Next: Library Explorer Import Error(DE-HDL)

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Hi, I updated to S008 today and am seeing a huge slow down in graphic speed with highlighting.

For example I have 11 parallel traces, if I pass the mouse across them at slow to moderate speed they do not highlight as would be expected. I have to actually land on the trace before it highlights.
The same thing is happening to other objects too like vias, Pins, symbols etc.

It looks like the S008 release has a bug, was wondering if anyone is seeing similar at their end and if a workaround exists ?.

Thanks.

Library Explorer Import Error(DE-HDL)

August 8, 2020, 11:49 am

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Hi, 

I am currently learning and using DE-HDL(17.2 ISR7) using Allegro PCB Designer(Schematic License).

One of our customers gave us DE-HDL Project file, and we have to revise its library and add our own in order to fabric PCB.

Unfortunately, as soon as I open library explorer, it give us error message "Library Explorer cannot be opened on design project. Hence, we cannot control library files on library explorer.

What do you think is the problem and solution? Your response should be appreciated!

Symptom is as the attached picture below:

 

Mouse scroll wheel won't pan

July 27, 2020, 7:56 am

≫ Next: Allegro EDM Flow Manager: error in cpm filed

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Hey Guys,

I got a new Logitech M500S mouse and the scroll won't pan when held down, it just zooms out. Anybody have a fix for this?

thanks!

Gary

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Allegro EDM Flow Manager: error in cpm filed

August 10, 2020, 5:01 am

≫ Next: Assigning net to copied Via+Cline? Alternate method for custom fanout?

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Does anyone know how to solve this issue? since my computer is upgraded automatically today then the issue's happened even though I reinstall the cadence tool.

Assigning net to copied Via+Cline? Alternate method for custom fanout?

August 10, 2020, 11:48 am

≫ Next: difference between solderpaste_top vs pastemask_top

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I'm in the process of laying out a series of DDR4 devices consisting of two ranks of five devices each. There will be a lot of repeated routing, even within the same device. Being as I want to match the trace lengths, I also want to match the tuned fanout at several pins. Some of the fanout is shown in the image below. The tuning is there to match other lengths within the DDR4's address bus.

I want to copy these Cline and vias to other pins within the routing of this device. 

Currently, if I copy the Via+Cline and move it to the pin I want it to connect to, it automatically assigns the Via+Cline to "GND". I assume this is because my ground plane is directly under this layer. Then, if I re-assign the net of the via to match the desired pin, the Cline goes to "No Net" and cannot be changed or modified - at least I don't see an option to assign a net to the dummy trace. I struggle to manually route a perfectly matched trace, so I am hoping to copy these traces.

After I complete the routing for the first device, I would like to copy the Clines and vias to the next device as this is a fly-by topology.

Is there a method for copying a Cline+Via, then re-assigning the net on the pasted Cline+Via? 

My tool set is OrCad PCB Designer Pro 17.4 S007.

difference between solderpaste_top vs pastemask_top

August 10, 2020, 12:16 pm

≫ Next: High Voltage Net Spacing

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Hello,

In the pad editor, I see the word "pastemask_top" for the steel sheet stencils for the solderpaste.When I open a .dra in Allegro, I see in the color dialog both pastemask_top and solderpaste_top.  I don't see solderpaste_top in the pad editor.

What is the solderpaste_top?

Frank

High Voltage Net Spacing

August 10, 2020, 12:35 pm

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I am laying out an isolated power supply PCB.  I would like to keep 3 high voltage nets on the input side of DC/DC converters spaced appropriately from the output side of the converters to prevent flashover.  In the constraints manager, I can set a spacing constraint for a particular net, but it creates that spacing and automatically modifies shapes associated with all of the other nets.  I would only like the tool to change shapes and give me DRC errors for a subset of the other nets.  It looks like I need to create a spacing CSET and then set the constraint for the 3 high voltage nets.  Has anyone done this?  Is this the way to do it.

Basically I want to keep nets x,y, and z 150 mils away from nets p, d, q, r, s, and t and not apply that constraint to any other nets.

Any help would be appreciated.

Thanks.

Shaune

Issue in Step file generation

August 11, 2020, 6:49 am

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I am having problem in one of the component in my PCB, this particular component always gets shifted to board origin when I generate the step file by export option. However the 3D canvas generated with in the ORCAD PCB is OK.

Attached are the images from 3D canvas generated in oracd PCB  (OK ) and step file created by export option (NG).