Im an engineering student and i am using Spice to model a single solar cell, but i am having some problems with it, i was wondering if someone can help me make this work, my problem is that the plot at the output is just a flat line i dont know why, i cant figure out what i am doing wrong.
When I import it goes until ".ends HCPL_3120". It seems to be a multi-whatever part.
When I import through IBIS translator (jut guessing) it creates several parts. Then I retouch HCPL_3120 in Captue->File->OpenLibrary ...I place it in circuit.
****** The line above is wrong, wat I was trying was file open directly to the *.txt Avago file ************
Well, pins 1 and 4 are NC. If I do not connect them, I get NET0075 unconnected pin. If I connect a ground (what should I?) I get in PSpice "Incorrect Number of Interface Nodes". (Just is case, I connect pins 6 and 7 together, these are the same output (parallel)).
This is quite annoying. I don't have a clue about this.
I was trying to replace a Resistance (345 ohm) and inductance(2.6mH) in series in my circuit with a Laplace model available in Pspice ABM Library. Since the Laplace for a RL circuit is R+Ls , I updated the 1/1+s as 1/345+0.0026s but the results obtained were not matching with the case where I was using the resistance and inductance components directly. Am I doing any mistakes in using this Laplace model? I would like to know whether anybody has used this previously,
I have a switch on a pcb which has a button cap placed on it. I created a round keepout to avoid placing components around the switch which will hit the button cap. I draw the actuator as a second placebound top for when I view the board in 3D. Since the actuator for the switch is higher than the keepout for the button cap I get a DRC error. Is it possible to layer the keepouts so I can place a higher keepout or "keepout void" within the button cap keepout or is the only way is to change the height of the switch actuator placebound top?
I'm doing a design in Design Entry HDL and importing into Allegro PCB Design L. (Versions 16.5). All of the multipinned parts import and place without issues. But I have some 1 pin parts, grounded mounting holes and fiducials, that give an error trying to place "E - Cannot load symbol 'xx'". There are no errors or warnings when exporting physical from the schematic. When importing into the PCB there are warnings "WARNING(SPMHNI-194): Symbol 'xx' for devide 'xx' not found in PSMPATH or must be "dbdoctor"ed.". The part symbols ARE in the PSMPATH along with all the other parts that placed without issue. Running the DBDOCTOR database check on the symbols and re-saving them doesn't make any difference.
Any clues as to why I can't load these parts? Thanks in advance.
I am doing the stability analysis (need to look at the amplitude response, phase response and phase delay) of an electronic circuit which will drive a DC motor (ofcourse its a closed loop system). The input to the circuit varies from +10 V to -10V and circuit contain opamp ELH0041. I am using ORCAD PSPICE for the modeling and would like to know, what kind of source model I can use for this analysis and what kind of analysis I should select from PSPICE.
Is there any way of manually adding a component to an Allegro PCB design using PCB Design XL in the same way that you could in OrCad Layout.
I have been able to copy a footprint but the component is unassigned (R*) and I cannot find how to assign it a new part number and to connect nets to it. In Layout, there was a feature that allowed you to add components and manually stitch nets to them.
I am new to PCB Editor 16.5 coming from Orcad Layout 15.7. I have been using Orcad products to do pcb layouts since it first came out back in the 80's. I would consider myself an expert user in Orcad Layout. I have found the transition to 16.5 to be nothing short of painful and I am looking for some guidance to help ease the pain..........
Any tips / lessons learned from folks that have successfully made this jump would be appreciated.
Are there any ways to rename the refdes of the parts with the same property(ie."connector=dual") which I specified during package the schematic? And do not change the refdes of the other parts without that property.
I am anew user oforcadpcbandwould like to knowifit is possible tominimizethe length of theratsnestduringthe placementof a component andnot after it isplaced.
I've opened up an existing brd file that I generated using OrCAD PCB Designer Professional v16.5. It appears that all of my parameters remained intact, however, the colors, transparency and brightness of the individual elements look different. Most of the differences aren't bad, they're just different.
The only problem I'm experiencing with this new color scheme is that my silk screen elements are almost completely invisible. You can't really see them unless you place your cursor over the silk screen element that you would like to see. I've even set the color of all of my silk screen elements to bright white in the Color192 screen and toyed with the transparency and shadow settings. The only way I can see the silk screen items is to supress all of the other elements and just enable the silk screen stuff. Even then, the color of the silk screen stuff is very muted and not very bright at all.
Has anyone else seen this or have an idea how to make the silk screen more visible or brighter?
OK - The "Snap To Grid" option simply doesn't work (for what I need) under 16.6 SP5. I obviously expect too much, but after several hours of clicking and reading the help docs, I can only conclude its broke. (please excuse the rant).
I'm trying to clean up a bunch items imported from dxf that ended up at weird off-grid coordinates, although basically close. The elements of concern just include mechanical features like circles, squares and panel outlines. I've successfully imported it to a brd file, but not surprisingly the coordinates are all screwed up from accuracy round-offs or whatever. Things were imported into the non-etch subclass "board_geometry/assembly_detail" for intended use as placement reference.
The problem arises in trying to clean it up a bit using the move > snap-to-grid command option. I have not been able to find a mouse click sequence that works (usefully) to get the drawing elements to align to my Allegro grid (non-etch), which is currently set to 1-mil. After several hours of playing around, I've managed to achieve alignment of a few elements, but not by using the "Snap To Grid" command option.
Any of the experts here have any insights into how Cadence intended this option to work? Is this a new UI productivity feature of 16.6 or do I just need to re-training? Also, discovering some help documentation (latest version installed) on "nudging" items a small amount, the "Shift-Click, Shift-Arrow" key method described doesn't work either. The folks writing the help files must be a few revs behind.
One issue might be with my imported circles that are interpreted by Allegro as single-line arcs (segments) with the same start/end point, and a center coordinate identified in the "show element" report. However there is "no origin" or "vertices" identifyable when tring to use the Move command, which is basically making the snap-to-grid option useless.
But it didn't work, I went to the (Install_dir)\tools\capture, there was no pxllite.ocx and truereuse.ocx but orpxllite.ocx and ortruereuse.ocx. I run them the same way as previous link, I did got "DllRegisterServer in orpxllite.ocx succeeded." and "DllRegisterServer in ortrueReuse.ocx succeeded." I still can't create netlist. I also trie to run capture "as a administrator", it can't work.
What i don't understand is if the pcb is just routed normally using
tracks and then there is a polygon placed on top to fill the board or if
the polygon(s) are used to connect components, also i do not understand
what the through holes are there for. Anything that could help me
understand this pcb is greatly appreciated. My goal is to reproduce this pcb, so anything that gets me going in that direction
(tutorials etc.) is greatly appreciated.
there is just explanation from Cadence Help about how can we use define via structure to duplicate via and cline we use frequently to do BGA fanout but there is no instruction on how do we able to delete those unused via structure? Does anyone over here know how to delete off those unwanted via structure? Thanks for help.
