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Difference between OrCAD EE Designer V16.6 and EE Designer Plus V16.6

March 18, 2013, 4:50 am
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Hi,

I was trying to purchase the professional version Pspice. Basically my present requirement is to perform some sort of stability analysis on a circuit which is not very complicated. Also need to do some tolerance analysis on the circuit. When I checked up, it looks like if I need to perform tolerance analysis I need to have Pspice Advanced Analysis version. Can anybody confirm this, because I was even able to perform a tolerance analysis with the Lite version, but there were restriction based on the number of components. Any info will be highly appreciated

Best regards

Madhuraj

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Dangling lines problem

March 18, 2013, 6:49 am
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 Hi All

Is there any way to delete all dangling lines @ one shot ...

 

Regards

Prashanth

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Orcad 9.2: Post Process Spreadsheet does not show any layers (outputs) ?

March 18, 2013, 5:41 am
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Hello,

In a recent PCB design using Orcad 9.2, when I open the Post Process Spreadsheet, no Layers (outputs) are visible, only the column headings are present.

Please see attached screenshot.



I compared with an older working design, and found that the older design had, in the Gerber Preferences, the 'Gerber Creation' group grayed out, while the faulty design did not have it grayed out.
 
I tried several things & fiddled with a few settings, to no avail. 

How can I get the ouputs / layers to show up in post process ?

Thank You. 
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Cost of Pspice A/D with Advanced Analysis

March 19, 2013, 3:51 am
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Hi

Does anyone know about the cost of Pspice A/D Licence with Advanced analysis option?

If Im not opting for the Advance Analysis option how much it will be?

Thanks for any info,

regards

Madhuraj

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How to make propety CDS_PHYS_NET_NAME invisible design entry HDL

March 19, 2013, 11:02 am
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Hi ,

In my  hierarchical design, the higher level net names are shoing up on the individual blocks as CDS_PHYS_NET_NAME property after packaging. 

How can I make it invisible. I tried using Format->Global property display , but  it only makes these property temporarly invisible. Once i make them invisible and save the page, I see that they appear back as soon as I browse to another  and then return back to the page.

Thanks

Ashok 

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Vertices or shape

March 19, 2013, 11:38 am
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Hello - What is best practice for the board outline, creating it as a shape or set of vertices?

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problems managing models with subcircuits and duplicate named parts

March 19, 2013, 11:03 am
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Hello, I am new at this, and trying to set up libraries with models.

I am currently working with two mosfet models downloaded fromSTmicro...both are subcircuit models with additional simple components modeled, and these simple components are named the same in each library and therefore wind up being "duplicate" models when both parts are in the library or design, therefore causing the modeling to be incorrectly applied between the parts. Here are the 2 models, seperated by "end of modelling" :

* MODELLING FOR STN2NF10
 
.SUBCKT STN2NF10 1 2 3
LG 2 4  7.5E-09
LS 12 3 7.5E-09
LD 6 1  4.5E-09
RG 4 5  4.001
RS 9 12 0.325E-02
RD 7 6  0.142
RJ 8 7  0.445E-03
CGS 5 9   0.419E-09
CGD 7 10  0.467E-09
CK  11 7  0.307E-10
DGD 11 7 DGD
DBS 12 6 DBS
DBD  9 7 DBD
MOS  13 5 9 9 MOS L=1u W=1u
E1  10 5 101 0 1
E2  11 5 102 0 1
E3  8 13 POLY(2) 6 8 6 12 0 0 0 0  0.321
G1  0 100 7 5 1u
D1  100 101  DID
D2  102 100  DID
R1  101 0  1MEG
R2  102 0  1MEG
.ENDS STN2NF10
 
.MODEL MOS NMOS
+ LEVEL = 3
+ VTO   = 4.184
+ PHI   = 0.827
+ IS    = 0.1E-12
+ JS    = 0
+ THETA = 0.995
+ KP    = 15.084
+ ETA   = 0.199E-02
 
.MODEL DGD D
+ IS    = 0.1E-12
+ CJO   = 0.171E-10
+ VJ    = 0.754
+ M     = 0.367
.MODEL DBD D
+ IS    = 0.1E-12
+ CJO   = 0.202E-10
+ VJ    = 0.755
+ M     = 0.335
.MODEL DBS D
+ IS    = 0.1E-12
+ BV    = 117
+ N     = 1
+ TT    = 0.699E-07
+ RS    = 0.505E-02
.MODEL DID D
+ IS    = 0.01E-12
+ RS    = 0
+ BV    = 127
 
* END OF MODELLING

* MODELLING FOR STN3NF06
.SUBCKT STN3NF06 1 2 3
LG 2 4  7.5n
LS 12 3 7.5n
LD 6 1  4.5n
RG 4 5  4.901
RS 9 12 0.321E-02
RD 7 6  0.301E-01
RJ 8 7  0.125E-02
CGS 5 9   0.474E-09
CGD 7 10  0.259E-09
CK  11 7  0.669E-10
DGD 11 7 DGD
DBS 12 6 DBS
DBD  9 7 DBD
MOS  13 5 9 9 MOS L=1u W=1u
E1  10 5 101 0 1
E2  11 5 102 0 1
E3  8 13 POLY(2) 6 8 6 12 0 0 0 0  0.778
G1  0 100 7 5 1u
D1  100 101  DID
D2  102 100  DID
R1  101 0  1MEG
R2  102 0  1MEG
.ENDS STN3NF06
 
.MODEL MOS NMOS
+ LEVEL = 3
+ VTO   = 3.867
+ PHI   = 0.941
+ IS    = 0.1P
+ JS    = 0
+ THETA = 0.375
+ KP    = 16.164
 
.MODEL DGD D
+ IS    = 0.1E-12
+ CJO   = 0.843E-11
+ VJ    = 0.697
+ M     = 0.389
.MODEL DBD D
+ IS    = 0.1E-12
+ CJO   = 0.248E-12
+ VJ    = 0.789
+ M     = 0.306
.MODEL DBS D
+ IS    = 0.1E-12
+ BV    = 65
+ N     = 1
+ TT    = 0.707E-07
+ RS    = 0.577E-01
.MODEL DID D
+ IS    = 0.01E-12
+ RS    = 0
+ BV    = 75
 
* END OF MODELLING

 As you can see, both models are using parts named nmos, dgd, dbd, and dbs.

Each mosfet will simulate correctly individually if the other library is not configured, but when both libraries are configured, the one part will use the parameters from the other instead of its own...for example the 1st mosfet should have a lower gain in an amplifier circuit, but with both libraries present it chooses the wrong parameters and has the higher gain of the 2nd mosfet instead. Help?

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BOM_IGNORE IN CAPTURE CIS-163

February 1, 2010, 4:36 pm
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 hi,

Is their an option where in i can generate a BOM while ignoring a component in the Schematic using Capture_CIS-163 something like wht it is in HDL

 

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Net Capacitance Constraint in the Constraint Manager

March 20, 2013, 9:11 am
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Hi,
I'm trying to check all nets in my design for the capacitance, just like Display->Parasitics show the capacitance to shield layer. With the "extracta" command I can do that for my whole design using a command file and the NET_CAPACITANCE attribute.

But how can I set up constraint in the constraint manager doing this?

What I'm looking for is something like the pre-defined "impedance" constraint that lets me specify a target impedance and a tolerance, but for the NET_CAPACITANCE.

(I'm using SPB 16.5-s039)  

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How is Net Resistance calculated?

March 20, 2013, 9:38 am
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I am curious how Allegro Physcal Viewer calculates a net's resistance. I can create a report which contains NET_RESISTANCE from the NET database. How is the value returned calculated? If the net is only a shape, does it calculate the resistance between the furthest points on that shape? Does it account for multiple layers or only one? Does it use an average width, or does it calculate the resistance of each segment and then add them up? If there are multiple source and sink pins, which ones does it select? Thanks.

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Allegro Free Physical Viewer 16.6 Will Not Run

March 20, 2013, 9:08 am
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I am bringing this to the community because I have not been able to get this resolved through Cadence support so here goes...

Back in early February, several product engineers running Windows 7 on Dell laptops at the large company I work at downloaded and installed Allegro Free Physical Viewer 16.6. We needed to upgrade to 16.6 to be able to open .brd created by our PCB layout group, who recently updated their layout tool. We use Allegro Free Physical Viewer to review PCB layouts prior to ordering them so it is important to be able to open them conveniently.

Since February 12, 2013, no one has been able to run Allegro Free Physical Viewer 16.6. There is an error screen at start up that says "The application has failed to start because its side-by-side configuration is incorrect. Please see the application event log or use the command-line sxstrace.exe tool for more detail." Because of this error, we have been unable to review files on our own PC. This is going on 5 weeks now.

Nothing we have done has fixed this. Cadence support has sent me to several websites to download 3rd party software patches ( http://www.microsoft.com/downloads/details.aspx?familyid=200B2FD9-AE1A-4A14-984D-389C36F85647&displaylang=en & http://www.microsoft.com/downloads/details.aspx?displaylang=en&FamilyID=766a6af7-ec73-40ff-b072-9112bab119c2) as well as download a patched(?) version of Allegro Free Physical Viewer at http://www.cadence.com/downloads/allegro/16.6/allegro_free_viewer_16-6.zip. None of these things have worked.

Has anyone else seen this problem? Has anyone solved this problem?

Thanks,

Kevin

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Viewing pcb footprint in schematic capture

March 20, 2013, 1:35 pm
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Hi

This was working sometime back.

We have had several updates and hotfixes and something now is not allowing me to view the footprints.

Anybody else having this issue and if you did, how did you fix it?

Thanks,

Carvey

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footprint script fail

March 20, 2013, 2:03 pm
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I have a problem when I want to import a footprint through Ultralibrarian software. Ultralibrarian exports a library including a script file to run at Allegro PCB software. The problem is that I run the script an error is produced. "Can't find window; Form.padedit"

Someone was happen some like that?

 regards

 

 

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Loading skill files

January 17, 2013, 12:41 am
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hi....

Is there a way to load skill files without using skill loader?

Thanks!

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SPECCTRA quit unexpectedly with an exit code of 3

March 26, 2010, 10:09 pm
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Hello all,

 I am new to PCB design and using examples from

Complete PCB design using OrCAD Capture and PCB editor book and when I try autorouter I am getting

 SPECCTRA quit unexpectedly with an exit code of 3. Please verify that you are running SPECCTRA version V9.0 or later. What am I doing wrong that I am getting this?

 

Best regards,

Fred

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Artwork Generation

January 20, 2010, 3:39 am
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Okay how do the pros set this up quickly? I find for each board it is a very tedious and painful process to get the correct folders set up and the classes and subclasses to get the silkscreen and soldermask and etch all setup.  I turn colors on and off in the workspace then add the folders and still find I work to do to get it all correct. In this regard I definately liked the simplicity of Layout but hope it's just operator ignorance. 

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Text not showing up in Gerbers after artwork generation

March 21, 2013, 1:56 pm
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If I see text when I set up my artwork why isn't it showing up in the Gerber layers?

This is labels inside of planes on the supplied default available film layers that are etch. The void in the plane is there but no text shows up.

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how can I define the ESR value to an inductor?

March 21, 2013, 9:15 am
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I placed a common inductor into the schematic. But I couldn't find the resistance attribute in the part property. For a comparison, by the LT-Spice, you can always edit the resistance value of an inductor with an easy right mouse click. I think it is much more intuitive.

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Using custom footprint ... not messing with the instalation

March 22, 2013, 5:35 am
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Hi.

I have the following custom footprint with files:

fp1.psm; fp1.dra; r411_367.pad

If I put these fles (I tested) in C:\Cadence\SPB_16.3\share\pcb\pcb_lib\symbolsfootprint the footprint will be shown in Capture->ShowFootprint.

The problem is that I don't want to mess around the installation that doesn't belong to me. I nees to keep my files out of the installation as much as possible.

Even so, I tried to mess with PCB Editor  (** my personal lib folder is H:/hm/proj/Electronica/_lib/PCB ***)

... so that:


set  padpath      = . symbols .. ../symbols C:/Cadence/SPB_16.3/share/local/pcb/padstacks C:/Cadence/SPB_16.3/share/pcb/pcb_lib/symbols C:/Cadence/SPB_16.3/share/pcb/allegrolib/symbols H:/hm/proj/Electronica/_lib/PCB

set  psmpath      = . symbols .. ../symbols C:/Cadence/SPB_16.3/share/local/pcb/symbols C:/Cadence/SPB_16.3/share/pcb/pcb_lib/symbols C:/Cadence/SPB_16.3/share/pcb/allegrolib/symbols H:/hm/proj/Electronica/_lib/PCB

... but still I can't convince Capture to find out the footprint if the filesare not located in C:\Cadence\SPB_16.3\share\pcb\pcb_lib\symbolsfootprint


Is there a way to convince Orcad Capture to find out my own lib's, specially footprints, messing around with the installation as less as possibe?

Thanks
Martins

 

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unknown problem during pcb generation

March 22, 2013, 4:14 am
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Hello, 

I encoutered a problem while netlisting and updating pcb desing.

I have a 16.6 capture desing with its pcb. Now I need to update few things in it, so I copied the desing to another folder, add few wires and netlist the desing, so far this is ok. After succesfull netlisting I updated the pcb, where input it the former pcb, and named it with new name (though the error is thrown with the same name too)

The error is displayed in the image link.

error

 

Netrev says:

(---------------------------------------------------------------------)
( )
( Allegro Netrev Import Logic )
( )
( Drawing : SK28LI11.brd )
( Software Version : 16.6S005 )
( Date/Time : Fri Mar 22 12:00:40 2013 )
( )
(---------------------------------------------------------------------)


------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/SK28LI11.brd';
NEW_BOARD_NAME 'SK28LI12.brd';

CmdLine: netrev.exe -y 1 -z -i G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro\SK28LI11.brd G:\ANALYZY\SKOP28T.1593\SKOP28LA\HW\SK28LI10\allegro\SK28LI12.brd

------ Preparing to read pst files ------

Starting to read G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstchip.dat
Finished reading G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstchip.dat (00:00:00.09)
Starting to read G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxprt.dat
Finished reading G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxprt.dat (00:00:00.01)
Starting to read G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxnet.dat
Finished reading G:/ANALYZY/SKOP28T.1593/SKOP28LA/HW/SK28LI10/allegro/pstxnet.dat (00:00:00.01)

------ Oversights/Warnings/Errors ------


#1 Run stopped because errors were detected

netrev run on Mar 22 12:00:40 2013
DESIGN NAME : 'SK28LI10'
PACKAGING ON Sep 10 2012 04:46:09

COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON

1 errors detected
No oversight detected
No warning detected

cpu time 1:05:06
elapsed time 0:00:39

--------------------------------------------------------------- end of netrev

 

Neither of this error outputs are very descriptive. No SAV is saved as mentioned in the error message, also dbdoctor on the pcb desing have not helped.

Would you please advice me how to solve this? We have no problem with this pcb updating so far. Could it be somehow connected with our recent update to 16.6. hotfix number 5 ?

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