Hi,
why required the internal layer trace width is wider than the external layer?
Thanks and regards,
Raam.
Hi,
why required the internal layer trace width is wider than the external layer?
Thanks and regards,
Raam.
Guess I get to be the one to resurrect this question Apparently you have to be in General Edit mode to select a via without automatically starting a Cline from it, so I am in General Edit Mode
I select the via, then go to the menus and select Edit > Change The only things in the Options panel that I can change are: Class, Subclass, Act via, Line Width, Text Block, and Text Just
There is no net option to select a net for the via to change to. I'm sure I'm missing something but I don't know what. I tried typing in the command line "editChangeNet -to AGND" (with and without quotes) and it returns an error "E- Command not found: editChangeNet -to AGND"
If I draw a track from a via with no net, it will assign itself to the net of the destination pin, but I'd like to be able to take a group of vias and either assign a net, or change the net that they're on in one step. Any clarification would be appreciated
Hi all,
New here and fairly new to OrCAD, currently studying on an Embedded Systems degree and we have been supplied Orcad 16.5 under a student license.
I am reasonably comfortable with building a circuit and running various simulations using components from the pspice library. And have got to a stage where I need to build a PCB, using the components that have come with OrCAD in the pspice library.
But I get a host of errors when I try to creat a netlist i.e. ERROR(ORCAP-36071): Illegal character "Forward Slash" etc. I can see clearly what the error is by looking in the terminal window, and am able to navigate to the componets Foot print value.
I have the circuit open in OrCAD Capture CIS, click on the .dsn file and then go to the tools menu and select Creat Netlist, then I tick the box Open Board in OrCAD PCB Editor.
Quite confused at this stage and have the following questions related to this:
1) Are there any library components supplied with Orcad that come with PCB Footprints that do not have this issue, or is this an error I am likely to get with certain libraries within OrCAD?
2) How can I identify what the valid footprint should be? (I know this is dependant on the component I use and relates to Question 3 I guess)
3) Is there a way I can preview all footprints so I can build a list up of known good ones for my circuits, then just copy paste from here to each component?
Thanks in-advance,
Ant
hi,
Is their an option where in i can generate a BOM while ignoring a component in the Schematic using Capture_CIS-163 something like wht it is in HDL
Anyone using Microsoft Access for their CIS database? That's what we are using but we would like a interface to limit the "hands on" access to the Access database. We are currently using an Excel based program that utilizes MathCAD (don't ask, I don't know), but it's not as functional as I would like. Anyone have any suggestions?
We currently have a process where one requests or creates the part and it gets saved in the database as "preliminary". Then someone checks it and it becomes "released". The "requester" and "approver" info gets saved into the database.
Thanks
Hi,
I am currently using Allegro 16.5. Pls let me know if there is any option to find out Via Capacitance .
Thanks
Bala R
Test Post
Hello all - I use PCB Editor on 3 different machines at various times of the week. I have my user preference for the display of my cursor set to "infinite". On two of the three machines I experience a "ghosting" of the cursor as I move it across the screen. A remnant of the cursor display is left until I pan or zoom. Any ideas what might be causing this? I'm guessing my graphics card. Thanks in advance.
Hi
I'm using PCB Editor 16.6 and routing a 6 layer board with several inner power and ground planes defined as dynamic fill copper shapes with the relevant nets attached.
I'm trying to slide clines which have top-to-bottom (not blind or buried) vias.
I find that the vias won't cross the inner layer shape boundaries smoothly and I certainly can't get a via to sit on top of the edge of the shape.
I can place a new via on a shape boundary but when I slide it later it just jumps to one side of the boundary or the other.
I've tried all sorts of settings of "slide" options and "shape" options like deferring dynamic fill, disabling DRC and so on without success.
So: any ideas on how I can get vias to slide smoothly across dynamic fill copper shape boundaries?
Thanks in anticipation...
Hi all,
When I'm generating 3D image of board for enclosure purpose the image appears like as in attached image. But it's not an exact image we can see after assembly of all parts, i mean an image like as a photo of the assembled board and the image is confusing the MCAD person. How can I generate an exact image in Allegro?
Thanks in advance,
Shiva.
I just upgraded to SPB16.6 My footprint viewer is no longer working in CIS. Any ideas? Thanks in advance.
I am bringing this to the community because I have not been able to get this resolved through Cadence support so here goes...
Back in early February, several product engineers running Windows 7 on Dell laptops at the large company I work at downloaded and installed Allegro Free Physical Viewer 16.6. We needed to upgrade to 16.6 to be able to open .brd created by our PCB layout group, who recently updated their layout tool. We use Allegro Free Physical Viewer to review PCB layouts prior to ordering them so it is important to be able to open them conveniently.
Since February 12, 2013, no one has been able to run Allegro Free Physical Viewer 16.6. There is an error screen at start up that says "The application has failed to start because its side-by-side configuration is incorrect. Please see the application event log or use the command-line sxstrace.exe tool for more detail." Because of this error, we have been unable to review files on our own PC. This is going on 5 weeks now.
Nothing we have done has fixed this. Cadence support has sent me to several websites to download 3rd party software patches ( http://www.microsoft.com/downloads/details.aspx?familyid=200B2FD9-AE1A-4A14-984D-389C36F85647&displaylang=en & http://www.microsoft.com/downloads/details.aspx?displaylang=en&FamilyID=766a6af7-ec73-40ff-b072-9112bab119c2) as well as download a patched(?) version of Allegro Free Physical Viewer at http://www.cadence.com/downloads/allegro/16.6/allegro_free_viewer_16-6.zip. None of these things have worked.
Has anyone else seen this problem? Has anyone solved this problem?
Thanks,
Kevin
hi frnds,
I hve a pblm while creating netlist...it shows so many errors...in session log,how to identify error?? in which place the error occur???
plz reply me!!!thankz n advance.......
Hi all,
New here and fairly new to OrCAD, currently studying on an Embedded Systems degree and we have been supplied Orcad 16.5 under a student license.
I am reasonably comfortable with building a circuit and running various simulations using components from the pspice library. And have got to a stage where I need to build a PCB, using the components that have come with OrCAD in the pspice library.
But I get a host of errors when I try to creat a netlist i.e. ERROR(ORCAP-36071): Illegal character "Forward Slash" etc. I can see clearly what the error is by looking in the terminal window, and am able to navigate to the componets Foot print value.
I have the circuit open in OrCAD Capture CIS, click on the .dsn file and then go to the tools menu and select Creat Netlist, then I tick the box Open Board in OrCAD PCB Editor.
Quite confused at this stage and have the following questions related to this:
1) Are there any library components supplied with Orcad that come with PCB Footprints that do not have this issue, or is this an error I am likely to get with certain libraries within OrCAD?
2) How can I identify what the valid footprint should be? (I know this is dependant on the component I use and relates to Question 3 I guess)
3) Is there a way I can preview all footprints so I can build a list up of known good ones for my circuits, then just copy paste from here to each component?
Thanks in-advance,
Ant
hi,
Is their an option where in i can generate a BOM while ignoring a component in the Schematic using Capture_CIS-163 something like wht it is in HDL
We sometimes need to define a thruhole via as a stack up of blind microvias and buried vias. This is becasue on th eTop and Bottom layers I need a smaller pad, that cannot be acieved with thruhole via, but only with blind micorvias. Is it possible in PCB Editor to define such a via, or at least to place a via over another in this way?
I'm an experienced self-taught on Orcad Layout 10.5, and I'm in the process to change to PCB Designer 16.6, and I find it very difficult to mentally 'translate' old Layout commands and names to PCB editor, they are so different!
Thanks in advance,
Leticia
Within the Dimensioning tool, how do you get a negative dimension to display on a value without having to use the external text function? I get the error ‘Dimension is only allowed to have a positive non-zero value’. It is necessary to have the negative displayed on the drawings.
In addition we also us a 2X for holes that are in line, so is that possible to add those without using the text function? Since they are used in separate tools, the ‘Move Text’ function in Dimension Environment will only move the number value and not the additional non-dimension text.
Thanks
Can someone explain in general what the definition of delta/tolerance is when adjusting for matched lengths in the constraint manager in Allegro? Thank you!