Hi all,
I'm trying to make my design more portable by keeping my padstacks for a new project away from the global library - is there a way I could open a symbol and save all the padstacks to some location?
I'm using PCB Editor (Allegro) 16.6, and there are A LOT of files generated when I'm doing things with these designs, and I'd like to know what I have to take and what is generated by the program.
Maybe I should write a skill file or tcl file to do this, if it doesn't exist?
Thanks!
We sometimes need to define a thruhole via as a stack up of blind microvias and buried vias. This is becasue on th eTop and Bottom layers I need a smaller pad, that cannot be acieved with thruhole via, but only with blind micorvias. Is it possible in PCB Editor to define such a via, or at least to place a via over another in this way?
I'm an experienced self-taught on Orcad Layout 10.5, and I'm in the process to change to PCB Designer 16.6, and I find it very difficult to mentally 'translate' old Layout commands and names to PCB editor, they are so different!
Thanks in advance,
Leticia
Did some simulation with high dynamic range (using a SUM ABM Model : adding a constant value of 1 with a sinus-wave having 120nV as amplitude) . I was supprized getting quantized data with a LSB of 60nV which corresponds to single precision (mantissa hase 23 + 1Bits). Is there any chance to get double precision?
Here my sim settings:
**** OPTION SUMMARY
******************************************************************************
OPTS
DC ANALYSIS -
ITL1 = 150
ITL2 = 20
RELTOL = 1.0000E-03
ABSTOL = 1.0000E-12
VNTOL = 1.0000E-09
GMIN = 1.0000E-12
VLTEXPLIMIT = .5
TRANSIENT ANALYSIS -
ITL4 = 10
TSTEPDIVFACTOR = 8
CHGTOL = 10.0000E-15
DMFACTOR = 1
FSTDELFACTOR = 1
MISCELLANEOUS -
NUMDGT = 10
WIDTH = 80
DEFL = 100.0000E-06
DEFW = 100.0000E-06
DEFAD = 0
DEFAS = 0
TNOM = 27
Thanks!
I am selecting a schematic entry tool for a PCB design that will have high speed serial technology PCIe Gen 3.0 and DDR3 and possibly blind and buried vias. It is my understanding that OrCad would NOT support the Constraints for HS, although easier to work with, and that Allegro Design Entry HDL is the tool required for these advanced technologies and applications?
What are the differences between these 2 schematic capture tools? What is the learning curve for an experienced PCB design engineer with Allegro HDL?
If I make a manual change to line width, the next net that I route should typically go back to Constraint, because the constraint generally determines the correct line width for all nets. So this new feature means more trips back to the Options tab, wasting time.
If I'm working with a partially-routed cline, I usually want to pick up the line width of that cline. This is also annoying because the retained line width isn't always (in fact, it usually isn't) the line width of the partially-routed cline. Again, I have to make a journey to the Options tab which slows down my progress. Sometimes the partially-routed line width is picked up, while other times the last-used line width is used; I haven't figured out what makes either condition occur.
I can think of two options to make my life easier:
Also, as I mentioned in the post linked above, I want to change line width with the mouse wheel during routing without losing PCB canvas area due to the Options tab being open. Assuming I can do that, this becomes even more of a problem because I now have the ability to change the line width with the Options tab closed, and I have no way to visually identify/confirm the current line width. Nor do I necessarily know what line width has been retained (I can guess and with fairly high accuracy, but there's no UI feature to show me for sure).
Hi guys perhaps you can help with this one.
I have located some title block .dra files in the PCB Symbols folder that I am working on at the moment. What I would like to be able to do is have "Text attributes" for the various entities within the title block such as a date field that auto updates to todays date.
In other PCB tools that I have used it is possible to have attributes for any text item you might want to change from one central menu. This is really handy because once you have stuff like ECO Number, Product number, Date etc defined in the title block you only have to go to one menu to update all those fields.
Basically what I am after is the same as what I can do in capture with title blocks but over on the PCB side of things.
One other thing is it possible to "fix" text items so they are fixed in place and cant be moved.
Thanks Scott.
Hi
i m Phd student i use the RF power BLF1822-10 mesurment but wen i use orcad to simulate the circuit i didnt find this transistor in laybrary
please if some one find this transistor send to me or haw i can find it
think'you for you'r help
tlig
How can I create the following Gerber files (RS-274x format) to send to a PCB prototyping factory:
I'm using Orcad Layout 16.0 to design my PCB board. When I create Extended Gerber files, I obtain the following files:
Hi,
I am facing problem in a dense board. me and my collegue working on a same board, he finishes routing on his part. When I merged both files there were unrouted nets showing on his part. I try drive connectivity and db doctor but problem is still there. kindly help me in this regards.
Best Regards
Tanveer
I'm using SPB 16.5 (soon 16.6) Design Entry HDL and Allegro PCB Design in Linux. When I load projmgr and load the design then click Design Entry the schematic comes up fine. When I click Layout the PCB Editor comes up blank. I need to go to recent designs and choose the board I'm working on. Is there a path variable or something to set so it will automatically come up with the correct board?
Also, I have quit and reload PCB Design every time to be able to get the full screen option. On the first load the top line of the window is off the screen and inaccessible. I just consider that a bug.
Thanks in advance.
Is there a way to resize the reference designators in PCB Design L? Text is easily resized in the schematic using F8 and F9 but I'm unable to find a corresponding function in the PCB editor.
Hi,
I had a design with wrong padstack on a footprint, which has already been place on a board and routed. I created a new and correct padstack named it as the old padstack after deleting the old padstack. Even after deleting and replacing the footprint on the board, the old padstack remain on the board and I cannot get it to be updated to the new padstack.
Can someone help as to how to update the wrong padstack to the new one?
Software: Allegro PCB Editor
Your comments are highly appreciated.
Aaron
Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;}Some time ago I recall some class/tutorial notes regarding the way SPB tools utilize these two subclasses with respect to component placement and constraints definitions as well as interpretation by the 3D viewer. I can't seem to locate those notes now.
I have always used place_bound shapes to represent actual component body dimensions and to create a crude 3D model for visualization of boards with components. With recent upgrade to 16.6, the footprint viewer (within CIS) does not properly interpret my footprints with the 3D heights.
I have noticed that in EMA supplied footprints, many also have dfa_bound shapes defined with height properties. Those footprints appear to reflect an appropriate 3D perspective in the CIS viewer.
Do I need to update all my symbol libraries to include both subclasses and/or why?
Oh - I've also noticed that the 3D viewer within symbol editor is still broken (since v16.3) with respect to inverting the Z-axis display of height information. The positive height properties are displayed downward through the board level padstacks as opposed to top-up. Anyone know of plans to "fix" that some day?
Any tutorial guidance is appreciated!
I want the edge-to-edge distance between these two pads, however whenever I select Dimension->Dimension Environment, then right click and select Linear Dimension, and select each of the pads, I keep getting the pin-to-pin dimension. What should I select in order to get a 'dumb' dimension?
I realize that I could take the pin-to-pin dimension, subtract half of the width of the rectangles on either side, and obtain my measurement, but I'm sure there's a way to do this automatically and I just don't know it (yet!)
Thanks!
I'm reading some tutorials and it seems to show moving or placing components rely strictly on the mouse cursor being snapped to a certain grid position....
is there a way to move or place components accurately without using the cursor? i.e. by typing in an exact coordinate value of where the pin or component needs to be placed?
many thanks
I am adding testponts to my board and want to use a smt on the bottom where ever poible.
I get "WARNING: Padstack TP35RD does not match the layer stackup ... REJECTED."
when adding the smt testpoint. why?
I am starting to build my first multilayer board and wish to know how to create a flash file, or how can I extract a flash file pattern from an existing board .brd file to my library.
Mike