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Vias in a symbol

March 14, 2014, 6:53 am
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I have a new dilemma this morning. I have an array of 30 vias that I need to embed in the tab of a TO package. My first curse of action was to add the VIA at the board. This led to inconsistent hookup to VIA, as little as 15 vias were hooked up out of a required 30. I tried dropping a shape over the vias to get them all to hook up but no go. There is also a requirement for a match shape on the bottom of the board. I went in the symbol level and attempted to add vias there. The tool promptly responded with DRCs(pad->pad) errors. How do I fix this? See attached picts, that will tell the story. I need to stick 30 vias onto pi4. Thanks.

-Ron Scott 

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Boundary

March 19, 2014, 11:51 am
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Gents,

I might be missing something painfully obvious but if you refer to the atached pict, I need to make  a PLACE_TOP_BOUNDARY and I need to hold to it's shape. I started out by putting in rectangle which was okay, It's the arc that's killing me. My plan was to build a shape with the arc component and then merge the resulting shapes and live happily ever after. Why can't I create a filled shape? See attached..

-Ron Scott 

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Fillets(teardrops)

March 21, 2014, 9:12 am
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Folks,

I'm trapped working with a bunch of mechanical engineers that have a penchant to implementing everything they read. My latest battle is that the MEs have read about fillets and want to utilize them right away. What's the forums view on fillets? Y/N I used them once years ago and don't any more. 

-Ron Scott 

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Create Via library

March 24, 2014, 5:45 am
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Gents,

I have been using a via set for years that will suit my needs. I'm sure every desigher here has there own set that  fulfills thier requirements. Having said all that; to  fulfill a request by my boss, I'd like to find out if there is a third party vendor that builds via libraries.

-Ron Scott

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need your help

March 23, 2014, 5:33 pm
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 I have been using Orcad 16.6, pcb editor for a while, everything works fine for me, I update license last week( add one more 16.6 licnese) . everything seems OK until I am trying to use artwork. after I click artwork, nothing happen.

 

I hope this is not license problem. but I really couldn't find out what happend to my system. it is a win7. 

I need release the design tomorrow, appreciate your help. 

 

David Sun

 

 

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Soldermask-to-Etch Clearance Check

March 24, 2014, 6:16 am
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I've set the spacing of "line to SMD Pin" to 0.5 millimeter as figure show below.

But,don't konw somehow the DRC check can't detect the error that the Etch overlap with soldermask of SMD Pin,figure show below.

Is there any way to make DRC error occure when the Etch overlap with soldermask of SMD Pin?

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How to avoid adding hundreds of nets one by one

March 23, 2014, 11:08 pm
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Hi experts,

 I am drawing a schematic with Capture, there are several large connectors in my schematic, I've already generated all nets needed in an excel, these nets are irregular. If I add these nets one by one, it will take me a long time and I can easily make mistakes.

Here is an example:

J1.1 --------------------- J2. 70               Net: data13

J1.2 ----------------------J2. 33               Net: data 9

.....................                                ......

J1.100 ------------------J2. 48               Net: data34

Could I import all the nets, which will be connected with a specific connector (e.g. J1), from an excel? 

Or, is there any other method to avoiding adding these nets one by one?

 

Thanks

Chris. 

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Aspect ratio

March 25, 2014, 2:01 am
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What is mean by aspect ratio in pcb design?
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3D STEP files

March 24, 2014, 6:16 am
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Folks,

On the infrequent occassion that I have to deal with mechanical stuff, I have been able to generate IDF files and send them off to my mechanical to use. I have now a new requirements to supply STEP models. I see the drop down in the tool but don't know how to uses it. Any gurus out there that can supply any good info ?

-Ron Scott

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Importing ConceptHDL 16.6 schematic into ConceptHDL 16.3 design

March 26, 2014, 2:43 am
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I am looking to reuse some of the existing design with the new design with from a newer version of the software. How can this be done?

 Thanks 

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PSPICE A/D - operations on two waveforms from two different simulations

March 26, 2014, 1:18 pm
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 I have two waveform: one V(I) at a temperature of -40°C and another one V(I) but at a different temperature, 85°C.

How can I make a 3rd waveform by substracting the two mentioned?

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library pointer

March 27, 2014, 1:32 pm
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Hi All,

Running SPB16.6. My current lib path is:

PSMPATH =  . 

           symbols 

           .. 

           ../symbols 

           C:/Cadence/SPB_16.6/share/local/pcb/symbols 

           C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols

 

PADPATH =  . 

           symbols 

           .. 

           ../symbols 

           C:/Cadence/SPB_16.6/share/local/pcb/padstacks 

           C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols 

           C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols 

           C:/learnallegro/padstacks/ 

 

My question is how can I set a different path for the PSM and PAD libs? Thanks!

Bob 

 

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.drl file generation reg.

February 23, 2012, 11:30 pm
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when generating NC drill file 'm getting the bellow error.

 

WARNING: Design precision is greater than that of the drill output file data.

Data rounding errors are very possible.

ERROR: The number of integer places specified for the

drill output data is not enough for this design.
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Hierarchical design

March 28, 2014, 4:54 am
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hi,

i have created a hierarchical design with many schematics inside it. Now i have to make a pdf of the design. And there is an order in which the pdf should be generated.

eg.

pages in schematic folder XX should come immediately after pages in BB folder.

i am unable to track in which order the pages are getting printed.

 is there any way to achieve that? please let me know

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Routing over voids

March 28, 2014, 2:15 pm
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Does Cadence have a function to help us indentify routing over voids and splits for high speed nets we care about?  If yes, where can i find it?

Thanks,

Patrick
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Learning Allegro

March 30, 2014, 10:19 pm
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There is any option available to learn allegro inbuilt?

 I found in Orcad, under help menu.But cadence not able to find.

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ERROR CAP0049

March 31, 2014, 5:48 am
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OrCAD CAPTURE 16.2

It is about to become me crazy.The following popup shows up every time I click on anywhere inside my schematic.

CAP0049

Errors were detected while reading a page. Please, open the page in the schematic editor and examine it to determine whether you wish to save the page in its current state.

File not found.

My design is composed by a TOP and 12 subcircuits which I instantiate hierarchically and more than once. I cant see any obvious error over the pages of my design.

Plase, I need help with this, I have spent 2 weeks seeking for this error. Thank you very much.

Ivan

 

 

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Create Via library

March 24, 2014, 5:45 am
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Gents,

I have been using a via set for years that will suit my needs. I'm sure every desigher here has there own set that  fulfills thier requirements. Having said all that; to  fulfill a request by my boss, I'd like to find out if there is a third party vendor that builds via libraries.

-Ron Scott

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PCB Design with a Microcontroller (Orcad Layout/Capture/PSpice)

March 31, 2014, 5:31 pm
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 Ok, I'm not trying to actually simulate a microcontroller in Pspice.  :)

But, I have designed a simple circuit that has a microcontroller at the heart, and I wanted to use the PCB design features to create the actual board for my circuit.

 My question is, how do I place the Microcontroller?  Do I simply use a different IC with the same package as my microcontroller, and route the traces to the appropriate pins?

Thanks for all of your help.

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strange Design Compare behavior

March 31, 2014, 6:34 pm
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 Hello,

 this is really strange to me,  I am using orcad 16.6,  I have an old layout design, there is a LED pin 2 ( D13.2) connected to ground. 

 for the pstxnet.dat file, under 

 NET_NAME 'GND'

................................................................................................

NODE_NAME    D13 2
 '@TOL-1371_SCH_R01.CONTROL MODULE(SCH_1):CONTROLLER BOARD@TOL-1371_SCH_R01.C1-CONTROLLER BOARD(SCH_1):MAIN CONTROLLER@TOL-1371_SCH_R01.C2-MAIN CONTROLLER(SCH_1):INS17176580@DISCRETE.LED.NORMAL(CHIPS)':
 'CATHODE':;

 

after I modified the design and clean up the liberary, the LED pin 2 still connected to ground. for new pstxnet.dat file,

 

NET_NAME
'GND'
 

.......................

NODE_NAME    D13 2
 '@TOL-1469.SCH, REV 01 SCH, SERENITY IV DEVELOPMENT BD.CONTROL MODULE(SCH_1):CONTROLLER BOARD@TOL-1469.SCH, REV 01 SCH, SERENITY IV DEVELOPMENT BD.C1-CONTROLLER BOARD(SCH_1):MAIN CONTROLLER@TOL-1469.SCH, REV 01 SCH, SERENITY IV DEVELOPMENT BD.C2-MAIN CONTROLLER(SCH_1):INS17176580@LED.LED_2.NORMAL(CHIPS)':
 'CATHODE':;
 

 the layout is based on old schematic. and  use import logic to update the net list to new desing. 

if I check the Design Compare for either old or new deisgn only, the D13.2 is in net GND, see following screen catch. but if I compare the old and new design together. the new design ( left side of the compare result) become D13.1, last screen catch. 

 something must be wrong. couldn't figure out. 

any suggestions are appreciate.

 

thanks,

 

David 

 

 

 

 

 

 

 

 

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