star point grounding

April 1, 2014, 12:30 am

≫ Next: Cadence Design Entry HDL connecting different widths buses

≪ Previous: strange Design Compare behavior

Hi @all!

I have a question concerning "star point grounding". Let me explain, what i mean: If i have two (or more) different grounds, let's say digital (DGND) and power (PGND), i want to keep them seperated from a connector until i reach a special point on the PCB, for example a microcontroller, where i want to connect both grounds.

To be able to connect both grounds, i have to create a connection in my schematic, right? But if i do so, it will result in just one net, connecting each point conntected either to DGND or PGND. How can i keep both nets seperated until i reach this special point? Especially with shapes ("GND-planes")?

To be clear: Of course, i can create two planes and creating voids around the pins of the "other GND", but i do have a connector with ~3.000 pins, at least half of them GND-pins. So i would prefer a clean solution - not a "hack" ;)

Thanks for your input!

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Cadence Design Entry HDL connecting different widths buses

April 1, 2014, 1:50 am

≫ Next: Transformer with 4 windings and nonlinear core

≪ Previous: star point grounding

Hi!

I use Cadence Design Entry HDL 16.5 for schematic entry. What I want to do is to connect four blocks(each has 16-bit bus input) to 64-bit bus. I know that for connecting single net to bus I use "tap". What component should I use to connect shorter bus (16-bit) to wider bus(64-bit)?

Regards,

Krzysztof

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Transformer with 4 windings and nonlinear core

April 1, 2014, 8:44 am

≫ Next: Cannot add a custom Via: (Type Unknown)

≪ Previous: Cadence Design Entry HDL connecting different widths buses

Hi,

I’m actually working on a step-up converter (see file attached) at the university. For further improvements I need a simulation of the converter. As you can see from the paper attached I have to implement a transformer with 4 windings: two primary and two secondary windings.

I tried to implement the transformer coupling four inductances with the part “K_linear”. Unfortunatelly the results didn’t really match with the measurements. For high input voltages (20mV to 30mV) the output voltages of the converter were to high, for low input voltages (10mV to 15mV) the transformer didn’t start up.

In my opinion this behaviour is strongly influenced by the core material of the transformer. Therefore I need a better model of the transformer. For the transformer I used a EP13 core (N87 core material). Could you please explain how a transformer with four windings and a specific core should be implemented? Could you give me some links to good tutorials on this topic?

Thanks in advance!

Simon

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Cannot add a custom Via: (Type Unknown)

April 1, 2014, 4:47 am

≫ Next: The Application has failed to start

≪ Previous: Transformer with 4 windings and nonlinear core

Hi,

I am now using the Cadence SPB 16.5. Employing the Pad Designer, I have made up a through hole via, I want to use this via in my PCB design. However, once I opened the constraint manager and add the built via, the constraint manager indicated that my pad(via) is an unknown type one:

Fig 1. unknown.png : VIA Type = Unknown

And the via is not availiable in my design.

How can I solve this problem?

Could you help me?

Naroah

Apr/01/2014

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The Application has failed to start

April 2, 2014, 11:51 am

≫ Next: Back Annotation Issue

≪ Previous: Cannot add a custom Via: (Type Unknown)

Error:

The Application has failed to start cdn_sfl401as.dll was not found. Please reinstall ...

while launching Orcad V16.6 Lite

I downloaded the zip and installed under XP Pro service Pack 3 using the Administrator account, and selected the All Users option.

Then loged out and back in with a user account but got that error when trying to fire it up.

Loged back out and fired it OK under the Administrator account. But I want it to work under any of the users as well. So I reinstalled it few times for no avail.

Now it is not even firing up under the Administrator account. it gives this error no mater which account I use.

here is the echo of my path

C:\Perl\site\bin;C:\Perl\bin;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\QuickTime\QTSystem\;
%CDSROOT%\tools\bin;
%CDSROOT%\tools\specctra\bin;
%CDSROOT%\tools\PSpice;
%CDSROOT%\tools\Capture;
%CDSROOT%\tools\fet\bin;
%CDSROOT%\tools\pcb\bin;
%CDSROOT%\OpenAccess\bin\win32\opt;

Many thx for helping.

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Back Annotation Issue

March 4, 2014, 9:52 pm

≫ Next: Problem placing multi-part schematic symbol in Allegro Design Entry

≪ Previous: The Application has failed to start

Hi,

While back annotating, I get an ERROR(SPCODD-549) in my swp.log file as follows,

#549 ERROR(SPCODD-549): No physical part found for COMP_DEVICE_TYPE=AD5232_TSSOP16_TSSOP16_IC_1.2MM, regenerate the netlist to sync
with Allegro board.
              ERROR(SPCODD-516): Line Number: 417
#549 ERROR(SPCODD-549): No physical part found for COMP_DEVICE_TYPE=ICL3232_SO16W_IC_2.65MM_312-806, regenerate the netlist to sync with Allegro board.
              ERROR(SPCODD-516): Line Number: 418
#549 ERROR(SPCODD-549): No physical part found for COMP_DEVICE_TYPE=XTAL_XTL_HC49SLF_IC_3.5MM_230-7, regenerate the netlist to sync with Allegro board.
              ERROR(SPCODD-516): Line Number: 419
#1 ERROR(ORCAP-36027): Unable to read physical netlist data.
#2 ERROR(ORCAP-36025): Aborting Swap file creation... Please correct the above errors and retry.

Please tell me how to resolve this issue.

Thanks.

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Problem placing multi-part schematic symbol in Allegro Design Entry

April 3, 2014, 10:23 am

≫ Next: PCB Editor | Netlist/refdes List Not Updating

≪ Previous: Back Annotation Issue

I just built a new schematic symbol using the spreadsheet entry method. It has 9 sections (Heterogeneous) and I can place sections B through I with no problem. When I attempt to place section A, I instead get one of the other sections (usually the one after the last one I placed).

Any idea what is causing this?

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PCB Editor | Netlist/refdes List Not Updating

April 3, 2014, 10:12 pm

≫ Next: [Done] why thermal reliefs in muti-layers board don't display ?

≪ Previous: Problem placing multi-part schematic symbol in Allegro Design Entry

Hello,

I am currently using Allegro Design Entry CIS 16.2 and am attempting to have it take my netlist and port it into PCB editor. Problem is, when I go to place parts, I notice that whenever I update my schematic, those updates are not being implemented into the PCB Editor. The only refdes names and schematic line connections remain while the new changes are nowhere to be seen.

Any ideas? I am also presented with a message when PCB Editor opens that states "WARNING(SPMHOD-33):Database was last saved by a higher tier tool…… Allegro Expert."

Any help is appreciated. Thanks!

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[Done] why thermal reliefs in muti-layers board don't display ?

April 4, 2014, 2:55 am

≫ Next: OrCad 9.2

≪ Previous: PCB Editor | Netlist/refdes List Not Updating

hi everyone,

I'm a beginner in PCB and I'm following this tutorial http://youtu.be/oGfvVkD_3lU

After pouring copper planes, we verify connectivity between pins and planes using thermal relief. In theory, there will be 4 situation:

Pic. 1 means you haven't cheked the Thermal pads option in Design Parameters, but after I check the option, I'm still in Pic 1. Does anyone have experience of this?

thanks

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OrCad 9.2

April 4, 2014, 6:47 am

≫ Next: Net Class to Dummy net spacing

≪ Previous: [Done] why thermal reliefs in muti-layers board don't display ?

Hi there,

I am getting this strange issue, which is about my OrCad 9.2 PCB Editor, unwanted VIAS and connectors occurs whenever I reopen the layout design after completing and closing my layout design, can anyone suggest me the casue of this strange error?

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Net Class to Dummy net spacing

April 4, 2014, 8:45 am

≫ Next: Symbols filter ON problem

≪ Previous: OrCad 9.2

Hi All,

I am looking for a way to set constraints between a Netclass I have to the dummy pins.

I have some high voltage area that requires much bigger spacing than rest of the circuit that is causing me some headache in getting the required spacing.

I would like to keep the default setting for lower voltage area and adjust the constraints by using net class to net class spacing.

I have grouped few nets to Net Class "A" and another set to Net Class "B". I am able to set the constraints so that spacing between default, "A", and "B" is what I want, but the spacing from "A" to Dummy net pins or "B" to Dummy net pins remains to be default setting.

Can anyone help me get these required spacing to these dummy nets?

I know using regions that we could get these results, but I would like to avoid the regions if possible for this case.

Thanks in advance.

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Symbols filter ON problem

April 4, 2014, 8:16 pm

≫ Next: Strange VIA behavior

≪ Previous: Net Class to Dummy net spacing

Hi,

When I am working in ORCAD or Allegro PCB editor and want to modify (Move, delete, change, etc..) anything with "Symbols" ON in "Design Object Find Filter" I see that ORCAD tries to draw many lines inside a component PAD repeatedly - where my curser is near it and I have greatly zoomed in - causing my PC slow down. It makes working with it very very difficult. I can't do anything evevn canceling the current command and I should only wait some seconds letting it draw those lines many times!.. I am using ORCAD16.5. Attached pictures show my problem, when my PC is busy doing this job it seems that software is crashed or stopped:

Symbols filter is ON

I would appreciate any help on this issue.

Thanks in advance,

Hossein

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Strange VIA behavior

April 5, 2014, 12:21 am

≫ Next: A simple question about PCB antenna?

≪ Previous: Symbols filter ON problem

Good Day

thanks in advance, :)

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A simple question about PCB antenna?

April 5, 2014, 1:48 pm

≫ Next: how create a ".cir" file in Orcad 16.3

≪ Previous: Strange VIA behavior

Have a question about PCB antenna in schematic.

I am doing a design which include a bluetooth PCB antenna.This pcb antenna is only a trace. I am wondering should I put a schematic symbol of antenna in schematic, and then make a footprint of PCB antenna? Or leaving it along in schematic, and routing a trace of antenna in PCB layout?

By the way, how to draw a trace in PCB layout, WITHOUT solder mask?

Thanks

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how create a ".cir" file in Orcad 16.3

April 6, 2014, 3:39 am

≫ Next: OrCAD 16.6 for Circuit Design

≪ Previous: A simple question about PCB antenna?

Hello,

I would like to create a "cir." file in Orcad 16.3 but I'm a little lost, is that you can help me?

is and what you can tell me how to change the number of output bipolar transistors, ie, I find in the software transistors 3 terminals (EBC), while I want to add the substrate channel but I do not know how. and when I change the netlest and I run the simulation it removes all the changes I did.

Thank you for your help.

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OrCAD 16.6 for Circuit Design

April 6, 2014, 8:33 am

≫ Next: ORCAP-1228: Part is out of date with design cache but cannot update cache to resolve.

≪ Previous: how create a ".cir" file in Orcad 16.3

Hi,

I am new to OrCAD and here are my queries:

Can I use OrCAD 16.6 for Circuit Design? as this software have some powerful tools like Capture & Capture CIS.
Do we need Virtuoso Schematic Editor for that?
What is the main difference between Capture & Capture CIS?
Can we simulate any kind of circuit in pspice?

Thanks in Advance.

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ORCAP-1228: Part is out of date with design cache but cannot update cache to resolve.

December 30, 2013, 2:04 pm

≫ Next: Export Artwork Control Form?

≪ Previous: OrCAD 16.6 for Circuit Design

When adding a part to a schematic, I sometimes get the error:

ERROR(ORCAP-1228): Part <part name> is out of date with respect to the design cache. Use Update Cache to synchronize the part in the cache with the library.

Where <part name> shows the name of the part I am trying to place. This seems to happen only when my database (I am using CIS) points to a symbol in a specific library - the MASTER_IC library. Other parts in the same database table, but pointing to a different schematic library, work fine.

After dismissing the error, the part will be placed. However if I place a different part that also has this problem, then try to place the first symbol again, it will not place the part even when dismissing the error. This time I will also get ORCIS-6184, and I cannot place the part.

What could be wrong with my MASTER_IC library causing this problem? If not a problem with the library, what could the problem be?

The error message says to update cache, but this does not help. This happens even when a completely blank design with nothing in the cache so I do not see how the part could really be out of date with a fresh design cache in the first place.

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Export Artwork Control Form?

April 7, 2014, 6:40 am

≫ Next: A problem I have encountered in Orcad Capture CIS,please help

≪ Previous: ORCAP-1228: Part is out of date with design cache but cannot update cache to resolve.

Is it possible to export a Artwork Control Form setup? I'm trying to avoid doing it manually.

Thanks

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A problem I have encountered in Orcad Capture CIS,please help

May 23, 2012, 6:02 am

≫ Next: Manufacturer's Boundary Recommendations

≪ Previous: Export Artwork Control Form?

Hi ,All

I'm using Allegro 16.3 and i'm having some troubles with Orcad Capture .

the following world will show this problem

--------------------------------------------------------------------------------------------------------------------------------------
The following 1 points have been identified as net connectivity change points from the last operation
--------------------------------------------------------------------------------------------------------------------------------------
(119.38, 30.48)

Any tips / lessons learned from folks that have successfully made this jump would be appreciated.

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Manufacturer's Boundary Recommendations

April 7, 2014, 10:17 am

≫ Next: I Cannot see the thermal relief and antipad on my GND plane.

≪ Previous: A problem I have encountered in Orcad Capture CIS,please help

All,

I'm in the need of information. I work in an environment that is geared toward the automotive industry. Typically, when I build a part, I'll also include a PLACE_BOUNDARY_XXX, which has a height attribute built in as well as making it more convenient for stuffing.. In previous job, multiple boards were built to fit in the same enclosure so height was very important. (<2'' boards). While having a discussion today, I was told by the ME that components will also spec a recommended boundary as opposed to just a recommended footprint. This revalation willl killl any library I might have, What information would the community have regarding the assertation that there are recommended boundaries are the norm? Brinf me out of the dark.

-Ron Scott

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