Hi all,
I am a beginner. i have drawn a schematic and created symbols as well. When I want to move components in PCB Editor or do any other modifications I see that software slows down in every step of grid and tries so many times to draw figures and shapes. Below video shows the problem, I am wondering how I can get a better performance and get rid of these all problems. I am using cadance 16.5
[Video]Hi,
I want to use Part Developer to create a pin with the bar above the pin name, for example, pin PC6 (RESET) of ATmega8 with the bar above RESET. In Design Entry CIS or some other capture tools, I can do it by adding some extra character, for example R\E\S\E\T\.
What I should do?
Thanks
Hi All,
Using 16.6-S.06 and Design Entry HDL.
I placed several resistors, caps, and inductors. When I look at the parts table for resistors, it looks like this in part:
DESCRIPTION VALUE COMP_PROPERTIES JEDEC_TYPE TOLERANCE RATED_POWER MATERIAL
res0201 0R 0R Res RESC0603X20N 0.05W Thickfilm
res0201_10R 10R Res RESC0603X20N 5% 0.05W Thickfilm
res0201_22R 22R Res RESC0603X20N 5% 0.05W Thickfilm
But if I select a part on the schematic and look at the attributes it looks like :
VALUE0R
LOCATIONRF_R410
PATHI57
PACK_TYPE<< NULL >>
TOLERANCE?
RATED_POWER?
RELEASE_STATUS?
JEDEC_TYPE?
MATERIAL?
$VARIANT?
My question is why do only the Key Properties transfer and not the Injected Properties? I have about 200 CAPS, RES, and IND with this problem. What's the easiest way to fix this so I can generate a netlist?
Thanks!
Bob
Hi,
I have a problem with dynamic shape on my board.
dynamic shapes on the board not updating even they are not voiding from any where. shape fill type is smooth and I try to update it from Display>Status>update dynamic shapes but error msg occured
"1 dynamic shape is still out of date or empty. Run Out of date shapes Report from status dialog to identify them."
I also try to DB doctor my pcb but not working. In the starting shape was fine Error occured suddenly I didnt know how it happens.
previously I have this problem and I resolved it by chance by removing internal plane layers from Xsection and again defined them. but I know this is not a proper solution.
Any Suggestions.
Regards
Tanveer
Hi, All, I want to make a new part (for example, some certain kind of mosfet), how to make it? By the way, I just start to learn this series of software. My version is 16.3. I would appreciate your help.
Hi!
I have to you the following question: how can I move the group of components or a single components by a defined offset? What should I type in the command window?
Best regards,
Krzysztof
Hello,
I designed a footprint that had a copper area obstacle that is correctly showing in the board design window but is not printed to the .xps file (I use an etching process for my boards). If I create an obstacle directly in the design window it is correctly printed. I would like to stress out that this: http://www.orcad.com/documents/community.faqs/layout/lay03088.aspx is not the problem because the copper area obstacle shows up in the board design window.
Thank you in advance,
Rúben
If I have a multi-parts(let's say 3 parts) component, I am placing them into schematic, it's labelled as U1A, U2A, U3A. I had to manually change U2A to U1B,and U3A to U1C so as to identify they are all from the same component. How does it automatically have labelled part as U1A, U1B, U1C? I cannot do that.
Also, if I continue to place parts such as U1A, U1B, U1C, U2A, U2B, U2C(again, I had manually to change it), how does it know U1A, U1B, U1C use the same footprint for layout and U2A,U2B, U2C use the same footprint?
Hi,
Is there a way to zoom in Allegro Design Entry Capture (ex OrCAD Capture) with mouse scroll only (i.e. without pressign Ctrl)?
Hi all,
I am using Orcad Capture CIS 16.5.
Can somebody please tell me how to change the "do not stuff" value for components not present in variants of the schematic?
Much like there are two symbols available for a resistor -- horizontal and vertical -- I have a second symbol for a part that I want to associate with the same package that already has one symbol associated with it. I have successfully created the symbol, but it is orphaned . . . it has no associated package (see attached image). I want to associate this new second symbol with the existing package. Have searched documentation and forums to no avail. Any suggestions?
Using Part Developer in Allegro DEHDL 16.5.
Hi,
I am new to the symbol creation in Concept HDL. I am stuck with 2 issue.
1.I had one small doubt regarding pin shape assigning. in HDl there is am option to slelct as single line or bubble shape. as attached in the below snap shot I want to add Bidirectional arrow mark for many pins. is there any automated way to do the same. please check the attached snapshot and let me know.
2. One more issue i am facing , I have created an FPGA symbol and i have arranged few pins. I want to retain this pin arrangement if i do some changes. how to retain this.
Hello,
I've got a problem with the 3D view of my board.
Several components have a bad rendering, the color is uniform on the component.
The component seem to be good when i'm in the package mapping tool and when i open the step file with an external step file viewer.
You can see on the following images a bad component (SMA) and a working component (0603 resistor).
The first image coming from an external step file viewer, the second is from the package mapping tool and the third is the 3D preview.
I've attached the step files if you want to try by yourself.
My Allegro version is 16.6 S020
Where do the problem come from?
Thanks,
Eric.
I am trying to create scheatic using Allegro Design Entry HDL (Version 16.5). I am learning this software since 2-3 days and I need help on how to edit the schematic description like <DRAWING_TITLE_HEADER>, <PRODUCT>, etc. (Please find corresponding image attached) I tried going to Tools>Options>Custom Variables, but I could not find any of the fields (or variable list) that correspond to this. Any help related to this would be appreciated.
Hi,
Seems I had a design rejected from the board house because I was missing the board outline on my artwork. So I checked it out and it was only on the bottom etch layer.
Apparently they need the outline on each layer.
Using allegro 16.5, I went to the artwork window and saw that the subclass board geometry/ outline was missing on ALL of the films, even the bottom one. So I added it to all layers, including the mask and silk layers.
I also checked the photoplot outline. It's present and larger than the board itself by about 1/2".
I cannot change the width of the outline. It's zero.
I even futzed with the undefined line width and shape bounding box and no dice, still no outline except on the bottom etch layer.
Can someone give me a hand here? I am not an expert here but I have a ton of designs to get out stat, since I am the only one left here.
Thanks in advance
Hi!
I have to you the following questions:
1) How do I define the new VIA so that I can use it later in Allegro? I know that I have to use the PAD Designer, but where I have to save the designed VIA so it is later visible in "Edit VIA List" within Constraint Manager in Allegro?
2) How I add to the layout a single VIA e.g. if I want to connect two planes together that are on different layers?
Best regards,
Krzysztof Sielewicz
Hi,
I am working with 16.5. I have three similar blocks - I've defined a property "Room" for components in Schematic - in my design. I have placed and routed one block in it's Room completely. Now, I'm wondering if there is a way that I can replicate those two other blocks just the same as first one? I mean something like a copy and pase. But, I want them to keep their corresponding net name or Ref Des which they have in Schematic. I saw something in 16.6 as module. But, I want to know what should I do in 16.5.
Thanks in advance,
Hossein